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b6cc0961b1
There are two major changes (and a few minor ones which are not listed here...see PR discussion for details) 1. Eigen::half implementations for HIP and CUDA have been merged. This means that - `CUDA/Half.h` and `HIP/hcc/Half.h` got merged to a new file `GPU/Half.h` - `CUDA/PacketMathHalf.h` and `HIP/hcc/PacketMathHalf.h` got merged to a new file `GPU/PacketMathHalf.h` - `CUDA/TypeCasting.h` and `HIP/hcc/TypeCasting.h` got merged to a new file `GPU/TypeCasting.h` After this change the `HIP/hcc` directory only contains one file `math_constants.h`. That will go away too once that file becomes a part of the HIP install. 2. new macros EIGEN_GPUCC, EIGEN_GPU_COMPILE_PHASE and EIGEN_HAS_GPU_FP16 have been added and the code has been updated to use them where appropriate. - `EIGEN_GPUCC` is the same as `(EIGEN_CUDACC || EIGEN_HIPCC)` - `EIGEN_GPU_DEVICE_COMPILE` is the same as `(EIGEN_CUDA_ARCH || EIGEN_HIP_DEVICE_COMPILE)` - `EIGEN_HAS_GPU_FP16` is the same as `(EIGEN_HAS_CUDA_FP16 or EIGEN_HAS_HIP_FP16)`
95 lines
3.0 KiB
C++
95 lines
3.0 KiB
C++
// This file is part of Eigen, a lightweight C++ template library
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// for linear algebra.
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//
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// Copyright (C) 2014 Benoit Steiner <benoit.steiner.goog@gmail.com>
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//
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// This Source Code Form is subject to the terms of the Mozilla
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// Public License v. 2.0. If a copy of the MPL was not distributed
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// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
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#ifndef EIGEN_CXX11_TENSOR_TENSOR_DEVICE_DEFAULT_H
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#define EIGEN_CXX11_TENSOR_TENSOR_DEVICE_DEFAULT_H
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namespace Eigen {
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// Default device for the machine (typically a single cpu core)
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struct DefaultDevice {
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void* allocate(size_t num_bytes) const {
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return internal::aligned_malloc(num_bytes);
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void deallocate(void* buffer) const {
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internal::aligned_free(buffer);
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void memcpy(void* dst, const void* src, size_t n) const {
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::memcpy(dst, src, n);
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void memcpyHostToDevice(void* dst, const void* src, size_t n) const {
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memcpy(dst, src, n);
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void memcpyDeviceToHost(void* dst, const void* src, size_t n) const {
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memcpy(dst, src, n);
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void memset(void* buffer, int c, size_t n) const {
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::memset(buffer, c, n);
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE size_t numThreads() const {
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#if !defined(EIGEN_GPU_COMPILE_PHASE)
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// Running on the host CPU
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return 1;
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#elif defined(EIGEN_HIP_DEVICE_COMPILE)
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// Running on a HIP device
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return 64;
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#else
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// Running on a CUDA device
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return 32;
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#endif
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE size_t firstLevelCacheSize() const {
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#if !defined(EIGEN_GPU_COMPILE_PHASE) && !defined(__SYCL_DEVICE_ONLY__)
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// Running on the host CPU
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return l1CacheSize();
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#elif defined(EIGEN_HIP_DEVICE_COMPILE)
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// Running on a HIP device
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return 48*1024; // FIXME : update this number for HIP
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#else
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// Running on a CUDA device, return the amount of shared memory available.
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return 48*1024;
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#endif
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE size_t lastLevelCacheSize() const {
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#if !defined(EIGEN_GPU_COMPILE_PHASE) && !defined(__SYCL_DEVICE_ONLY__)
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// Running single threaded on the host CPU
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return l3CacheSize();
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#elif defined(EIGEN_HIP_DEVICE_COMPILE)
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// Running on a HIP device
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return firstLevelCacheSize(); // FIXME : update this number for HIP
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#else
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// Running on a CUDA device
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return firstLevelCacheSize();
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#endif
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE int majorDeviceVersion() const {
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#if !defined(EIGEN_GPU_COMPILE_PHASE)
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// Running single threaded on the host CPU
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// Should return an enum that encodes the ISA supported by the CPU
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return 1;
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#elif defined(EIGEN_HIP_DEVICE_COMPILE)
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// Running on a HIP device
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// return 1 as major for HIP
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return 1;
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#else
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// Running on a CUDA device
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return EIGEN_CUDA_ARCH / 100;
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#endif
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}
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};
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} // namespace Eigen
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#endif // EIGEN_CXX11_TENSOR_TENSOR_DEVICE_DEFAULT_H
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