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[PATCH 1/2] Misc. typos
From 68d431b4c14ad60a778ee93c1f59ecc4b931950e Mon Sep 17 00:00:00 2001 Found via `codespell -q 3 -I ../eigen-word-whitelist.txt` where the whitelists consists of: ``` als ans cas dum lastr lowd nd overfl pres preverse substraction te uint whch ``` --- CMakeLists.txt | 26 +++++++++---------- Eigen/src/Core/GenericPacketMath.h | 2 +- Eigen/src/SparseLU/SparseLU.h | 2 +- bench/bench_norm.cpp | 2 +- doc/HiPerformance.dox | 2 +- doc/QuickStartGuide.dox | 2 +- .../Eigen/CXX11/src/Tensor/TensorChipping.h | 6 ++--- .../Eigen/CXX11/src/Tensor/TensorDeviceGpu.h | 2 +- .../src/Tensor/TensorForwardDeclarations.h | 4 +-- .../src/Tensor/TensorGpuHipCudaDefines.h | 2 +- .../Eigen/CXX11/src/Tensor/TensorReduction.h | 2 +- .../CXX11/src/Tensor/TensorReductionGpu.h | 2 +- .../test/cxx11_tensor_concatenation.cpp | 2 +- unsupported/test/cxx11_tensor_executor.cpp | 2 +- 14 files changed, 29 insertions(+), 29 deletions(-)
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@@ -244,7 +244,7 @@ struct TensorEvaluator<const TensorChippingOp<DimId, ArgType>, Device>
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return rslt;
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} else if ((static_cast<int>(Layout) == static_cast<int>(ColMajor) && m_dim.actualDim() == NumInputDims - 1) ||
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(static_cast<int>(Layout) == static_cast<int>(RowMajor) && m_dim.actualDim() == 0)) {
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// m_stride is aways greater than index, so let's avoid the integer division.
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// m_stride is always greater than index, so let's avoid the integer division.
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eigen_assert(m_stride > index);
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return m_impl.template packet<LoadMode>(index + m_inputOffset);
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} else {
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@@ -377,7 +377,7 @@ struct TensorEvaluator<const TensorChippingOp<DimId, ArgType>, Device>
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inputIndex = index * m_inputStride + m_inputOffset;
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} else if ((static_cast<int>(Layout) == static_cast<int>(ColMajor) && m_dim.actualDim() == NumInputDims - 1) ||
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(static_cast<int>(Layout) == static_cast<int>(RowMajor) && m_dim.actualDim() == 0)) {
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// m_stride is aways greater than index, so let's avoid the integer
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// m_stride is always greater than index, so let's avoid the integer
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// division.
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eigen_assert(m_stride > index);
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inputIndex = index + m_inputOffset;
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@@ -462,7 +462,7 @@ struct TensorEvaluator<TensorChippingOp<DimId, ArgType>, Device>
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}
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} else if ((static_cast<int>(this->Layout) == static_cast<int>(ColMajor) && this->m_dim.actualDim() == NumInputDims-1) ||
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(static_cast<int>(this->Layout) == static_cast<int>(RowMajor) && this->m_dim.actualDim() == 0)) {
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// m_stride is aways greater than index, so let's avoid the integer division.
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// m_stride is always greater than index, so let's avoid the integer division.
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eigen_assert(this->m_stride > index);
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this->m_impl.template writePacket<StoreMode>(index + this->m_inputOffset, x);
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} else {
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@@ -12,7 +12,7 @@
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// This header file container defines fo gpu* macros which will resolve to
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// their equivalent hip* or cuda* versions depending on the compiler in use
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// A separte header (included at the end of this file) will undefine all
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// A separate header (included at the end of this file) will undefine all
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#include "TensorGpuHipCudaDefines.h"
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namespace Eigen {
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@@ -25,9 +25,9 @@ template<typename T> struct MakePointer {
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};
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// The PointerType class is a container of the device specefic pointer
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// used for refering to a Pointer on TensorEvaluator class. While the TensorExpression
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// used for referring to a Pointer on TensorEvaluator class. While the TensorExpression
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// is a device-agnostic type and need MakePointer class for type conversion,
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// the TensorEvaluator calss can be specialized for a device, hence it is possible
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// the TensorEvaluator calls can be specialized for a device, hence it is possible
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// to construct different types of temproray storage memory in TensorEvaluator
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// for different devices by specializing the following PointerType class.
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template<typename T, typename Device> struct PointerType : MakePointer<T>{};
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@@ -16,7 +16,7 @@
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// for some reason gets sent to the gcc/host compiler instead of the gpu/nvcc/hipcc compiler
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// When compiling such files, gcc will end up trying to pick up the CUDA headers by
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// default (see the code within "unsupported/Eigen/CXX11/Tensor" that is guarded by EIGEN_USE_GPU)
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// This will obsviously not work when trying to compile tensorflow on a sytem with no CUDA
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// This will obsviously not work when trying to compile tensorflow on a system with no CUDA
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// To work around this issue for HIP systems (and leave the default behaviour intact), the
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// HIP tensorflow build defines EIGEN_USE_HIP when compiling all source files, and
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// "unsupported/Eigen/CXX11/Tensor" has been updated to use HIP header when EIGEN_USE_HIP is
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@@ -965,7 +965,7 @@ struct TensorEvaluator<const TensorReductionOp<Op, Dims, ArgType, MakePointer_>,
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}
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}
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// Intialize output coefficient reducers.
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// Initialize output coefficient reducers.
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for (int i = 0; i < num_reducers; ++i) {
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new (&reducers[i]) BlockReducer(m_reducer);
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}
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@@ -771,7 +771,7 @@ struct OuterReducer<Self, Op, GpuDevice> {
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// terminate called after throwing an instance of 'std::runtime_error'
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// what(): No device code available for function: _ZN5Eigen8internal20OuterReductionKernelIL...
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//
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// dont know why this happens (and why is it a runtime error instead of a compile time errror)
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// don't know why this happens (and why is it a runtime error instead of a compile time error)
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//
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// this will be fixed by HIP PR#457
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EIGEN_DEVICE_FUNC
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