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[SYCL] This PR adds the minimum modifications to the Eigen unsupported module required to run it on devices supporting SYCL.
* Abstracting the pointer type so that both SYCL memory and pointer can be captured. * Converting SYCL virtual pointer to SYCL device memory in Eigen evaluator class. * Binding SYCL placeholder accessor to command group handler by using bind method in Eigen evaluator node. * Adding SYCL macro for controlling loop unrolling. * Modifying the TensorDeviceSycl.h and SYCL executor method to adopt the above changes.
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@@ -37,7 +37,7 @@ namespace {
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{
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#ifdef EIGEN_GPU_COMPILE_PHASE
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return __clz(val);
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#elif defined(__SYCL_DEVICE_ONLY__)
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#elif defined(SYCL_DEVICE_ONLY)
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return cl::sycl::clz(val);
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#elif EIGEN_COMP_MSVC
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unsigned long index;
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@@ -55,8 +55,8 @@ namespace {
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{
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#ifdef EIGEN_GPU_COMPILE_PHASE
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return __clzll(val);
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#elif defined(__SYCL_DEVICE_ONLY__)
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return cl::sycl::clz(val);
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#elif defined(SYCL_DEVICE_ONLY)
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return static_cast<int>(cl::sycl::clz(val));
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#elif EIGEN_COMP_MSVC && EIGEN_ARCH_x86_64
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unsigned long index;
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_BitScanReverse64(&index, val);
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@@ -92,7 +92,7 @@ namespace {
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EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE uint32_t muluh(const uint32_t a, const T b) {
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#if defined(EIGEN_GPU_COMPILE_PHASE)
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return __umulhi(a, b);
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#elif defined(__SYCL_DEVICE_ONLY__)
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#elif defined(SYCL_DEVICE_ONLY)
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return cl::sycl::mul_hi(a, static_cast<uint32_t>(b));
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#else
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return (static_cast<uint64_t>(a) * b) >> 32;
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@@ -103,7 +103,7 @@ namespace {
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EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE uint64_t muluh(const uint64_t a, const T b) {
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#if defined(EIGEN_GPU_COMPILE_PHASE)
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return __umul64hi(a, b);
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#elif defined(__SYCL_DEVICE_ONLY__)
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#elif defined(SYCL_DEVICE_ONLY)
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return cl::sycl::mul_hi(a, static_cast<uint64_t>(b));
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#elif defined(__SIZEOF_INT128__)
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__uint128_t v = static_cast<__uint128_t>(a) * static_cast<__uint128_t>(b);
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@@ -124,7 +124,7 @@ namespace {
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template <typename T>
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struct DividerHelper<64, T> {
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static EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE uint64_t computeMultiplier(const int log_div, const T divider) {
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#if defined(__SIZEOF_INT128__) && !defined(EIGEN_GPU_COMPILE_PHASE) && !defined(__SYCL_DEVICE_ONLY__)
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#if defined(__SIZEOF_INT128__) && !defined(EIGEN_GPU_COMPILE_PHASE) && !defined(SYCL_DEVICE_ONLY)
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return static_cast<uint64_t>((static_cast<__uint128_t>(1) << (64+log_div)) / static_cast<__uint128_t>(divider) - (static_cast<__uint128_t>(1) << 64) + 1);
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#else
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const uint64_t shift = 1ULL << log_div;
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@@ -205,8 +205,8 @@ class TensorIntDivisor<int32_t, true> {
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EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE int divide(const int32_t n) const {
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#ifdef EIGEN_GPU_COMPILE_PHASE
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return (__umulhi(magic, n) >> shift);
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#elif defined(__SYCL_DEVICE_ONLY__)
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return (cl::sycl::mul_hi(static_cast<uint64_t>(magic), static_cast<uint64_t>(n)) >> shift);
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#elif defined(SYCL_DEVICE_ONLY)
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return (cl::sycl::mul_hi(magic, static_cast<uint32_t>(n)) >> shift);
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#else
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uint64_t v = static_cast<uint64_t>(magic) * static_cast<uint64_t>(n);
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return (static_cast<uint32_t>(v >> 32) >> shift);
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