2010-07-10 00:09:29 +03:00
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// This file is part of Eigen, a lightweight C++ template library
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// for linear algebra.
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//
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// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>
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2016-04-28 14:32:11 -03:00
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// Copyright (C) 2010 Konstantinos Margaritis <markos@freevec.org>
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2010-07-10 00:09:29 +03:00
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//
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2012-07-13 14:42:47 -04:00
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// This Source Code Form is subject to the terms of the Mozilla
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// Public License v. 2.0. If a copy of the MPL was not distributed
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// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
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2010-07-10 00:09:29 +03:00
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2010-10-25 10:15:22 -04:00
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#ifndef EIGEN_COMPLEX_NEON_H
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#define EIGEN_COMPLEX_NEON_H
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2010-07-10 00:09:29 +03:00
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2012-04-15 11:06:28 +01:00
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namespace Eigen {
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2010-10-25 10:15:22 -04:00
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namespace internal {
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2016-06-28 11:12:49 -04:00
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inline uint32x4_t p4ui_CONJ_XOR() {
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2016-10-12 16:55:47 +02:00
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// See bug 1325, clang fails to call vld1q_u64.
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#if EIGEN_COMP_CLANG
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uint32x4_t ret = { 0x00000000, 0x80000000, 0x00000000, 0x80000000 };
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return ret;
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#else
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2016-06-28 11:12:49 -04:00
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static const uint32_t conj_XOR_DATA[] = { 0x00000000, 0x80000000, 0x00000000, 0x80000000 };
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return vld1q_u32( conj_XOR_DATA );
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2016-10-12 16:55:47 +02:00
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#endif
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2016-06-28 11:12:49 -04:00
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}
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inline uint32x2_t p2ui_CONJ_XOR() {
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static const uint32_t conj_XOR_DATA[] = { 0x00000000, 0x80000000 };
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return vld1_u32( conj_XOR_DATA );
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}
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2010-07-10 00:09:29 +03:00
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//---------- float ----------
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struct Packet2cf
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{
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EIGEN_STRONG_INLINE Packet2cf() {}
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EIGEN_STRONG_INLINE explicit Packet2cf(const Packet4f& a) : v(a) {}
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Packet4f v;
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};
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2010-10-25 10:15:22 -04:00
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template<> struct packet_traits<std::complex<float> > : default_packet_traits
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2010-07-10 00:09:29 +03:00
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{
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typedef Packet2cf type;
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2014-03-28 10:18:04 +01:00
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typedef Packet2cf half;
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2010-07-10 00:09:29 +03:00
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enum {
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Vectorizable = 1,
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2011-05-06 09:03:48 +02:00
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AlignedOnScalar = 1,
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2010-07-10 00:09:29 +03:00
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size = 2,
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2014-10-22 07:39:49 +00:00
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HasHalfPacket = 0,
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2010-07-10 00:09:29 +03:00
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HasAdd = 1,
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HasSub = 1,
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HasMul = 1,
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HasDiv = 1,
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HasNegate = 1,
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HasAbs = 0,
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HasAbs2 = 0,
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HasMin = 0,
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HasMax = 0,
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HasSetLinear = 0
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};
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};
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Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
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template<> struct unpacket_traits<Packet2cf> { typedef std::complex<float> type; enum {size=2, alignment=Aligned16, vectorizable=true, masked_load_available=false}; typedef Packet2cf half; };
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2010-07-10 00:09:29 +03:00
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf pset1<Packet2cf>(const std::complex<float>& from)
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2010-07-10 00:09:29 +03:00
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{
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float32x2_t r64;
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2018-04-18 18:46:34 +02:00
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r64 = vld1_f32((const float *)&from);
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2010-07-10 00:09:29 +03:00
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return Packet2cf(vcombine_f32(r64, r64));
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf padd<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(padd<Packet4f>(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet2cf psub<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(psub<Packet4f>(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet2cf pnegate(const Packet2cf& a) { return Packet2cf(pnegate<Packet4f>(a.v)); }
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template<> EIGEN_STRONG_INLINE Packet2cf pconj(const Packet2cf& a)
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2010-07-10 00:09:29 +03:00
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{
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2010-12-10 20:27:46 +02:00
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Packet4ui b = vreinterpretq_u32_f32(a.v);
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2016-06-28 11:12:49 -04:00
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return Packet2cf(vreinterpretq_f32_u32(veorq_u32(b, p4ui_CONJ_XOR())));
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2010-07-10 00:09:29 +03:00
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf pmul<Packet2cf>(const Packet2cf& a, const Packet2cf& b)
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2010-07-10 00:09:29 +03:00
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{
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Packet4f v1, v2;
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// Get the real values of a | a1_re | a1_re | a2_re | a2_re |
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v1 = vcombine_f32(vdup_lane_f32(vget_low_f32(a.v), 0), vdup_lane_f32(vget_high_f32(a.v), 0));
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2015-12-10 16:06:33 +01:00
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// Get the imag values of a | a1_im | a1_im | a2_im | a2_im |
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2010-07-10 00:09:29 +03:00
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v2 = vcombine_f32(vdup_lane_f32(vget_low_f32(a.v), 1), vdup_lane_f32(vget_high_f32(a.v), 1));
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// Multiply the real a with b
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v1 = vmulq_f32(v1, b.v);
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// Multiply the imag a with b
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v2 = vmulq_f32(v2, b.v);
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// Conjugate v2
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2016-06-28 11:12:49 -04:00
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v2 = vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(v2), p4ui_CONJ_XOR()));
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2010-07-10 00:09:29 +03:00
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// Swap real/imag elements in v2.
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2013-06-10 15:59:03 +02:00
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v2 = vrev64q_f32(v2);
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2010-07-10 00:09:29 +03:00
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// Add and return the result
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return Packet2cf(vaddq_f32(v1, v2));
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}
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2019-02-21 13:32:13 -08:00
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template<> EIGEN_STRONG_INLINE Packet2cf pcmp_eq(const Packet2cf& a, const Packet2cf& b)
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{
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// Compare real and imaginary parts of a and b to get the mask vector:
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// [re(a[0])==re(b[0]), im(a[0])==im(b[0]), re(a[1])==re(b[1]), im(a[1])==im(b[1])]
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Packet4f eq = pcmp_eq<Packet4f>(a.v, b.v);
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// Swap real/imag elements in the mask in to get:
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// [im(a[0])==im(b[0]), re(a[0])==re(b[0]), im(a[1])==im(b[1]), re(a[1])==re(b[1])]
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Packet4f eq_swapped = vrev64q_f32(eq);
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// Return re(a)==re(b) && im(a)==im(b) by computing bitwise AND of eq and eq_swapped
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return Packet2cf(pand<Packet4f>(eq, eq_swapped));
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf pand <Packet2cf>(const Packet2cf& a, const Packet2cf& b)
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2010-07-10 00:09:29 +03:00
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{
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2014-10-22 07:39:49 +00:00
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return Packet2cf(vreinterpretq_f32_u32(vandq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));
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2010-07-10 00:09:29 +03:00
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf por <Packet2cf>(const Packet2cf& a, const Packet2cf& b)
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2010-07-10 00:09:29 +03:00
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{
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return Packet2cf(vreinterpretq_f32_u32(vorrq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf pxor <Packet2cf>(const Packet2cf& a, const Packet2cf& b)
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2010-07-10 00:09:29 +03:00
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{
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return Packet2cf(vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf pandnot<Packet2cf>(const Packet2cf& a, const Packet2cf& b)
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2010-07-10 00:09:29 +03:00
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{
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return Packet2cf(vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));
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}
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2010-12-10 20:27:46 +02:00
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template<> EIGEN_STRONG_INLINE Packet2cf pload<Packet2cf>(const std::complex<float>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet2cf(pload<Packet4f>((const float*)from)); }
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template<> EIGEN_STRONG_INLINE Packet2cf ploadu<Packet2cf>(const std::complex<float>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet2cf(ploadu<Packet4f>((const float*)from)); }
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2010-07-10 00:09:29 +03:00
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2011-02-23 16:31:42 +01:00
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template<> EIGEN_STRONG_INLINE Packet2cf ploaddup<Packet2cf>(const std::complex<float>* from) { return pset1<Packet2cf>(*from); }
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float> * to, const Packet2cf& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((float*)to, from.v); }
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template<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float> * to, const Packet2cf& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((float*)to, from.v); }
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2010-07-10 00:09:29 +03:00
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2015-02-16 15:05:41 +01:00
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template<> EIGEN_DEVICE_FUNC inline Packet2cf pgather<std::complex<float>, Packet2cf>(const std::complex<float>* from, Index stride)
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2014-04-17 12:28:01 -07:00
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{
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2015-05-15 11:15:53 -04:00
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Packet4f res = pset1<Packet4f>(0.f);
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2014-04-17 12:28:01 -07:00
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res = vsetq_lane_f32(std::real(from[0*stride]), res, 0);
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res = vsetq_lane_f32(std::imag(from[0*stride]), res, 1);
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res = vsetq_lane_f32(std::real(from[1*stride]), res, 2);
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res = vsetq_lane_f32(std::imag(from[1*stride]), res, 3);
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return Packet2cf(res);
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}
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2015-02-16 15:05:41 +01:00
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template<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet2cf>(std::complex<float>* to, const Packet2cf& from, Index stride)
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2014-04-17 12:28:01 -07:00
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{
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to[stride*0] = std::complex<float>(vgetq_lane_f32(from.v, 0), vgetq_lane_f32(from.v, 1));
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to[stride*1] = std::complex<float>(vgetq_lane_f32(from.v, 2), vgetq_lane_f32(from.v, 3));
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}
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2018-04-18 18:46:34 +02:00
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template<> EIGEN_STRONG_INLINE void prefetch<std::complex<float> >(const std::complex<float> * addr) { EIGEN_ARM_PREFETCH((const float *)addr); }
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2010-07-10 00:09:29 +03:00
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE std::complex<float> pfirst<Packet2cf>(const Packet2cf& a)
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2010-07-10 00:09:29 +03:00
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{
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2019-01-14 21:45:56 +01:00
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EIGEN_ALIGN16 std::complex<float> x[2];
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2010-07-10 00:09:29 +03:00
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vst1q_f32((float *)x, a.v);
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return x[0];
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}
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2010-10-25 10:15:22 -04:00
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template<> EIGEN_STRONG_INLINE Packet2cf preverse(const Packet2cf& a)
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2010-07-10 00:09:29 +03:00
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{
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float32x2_t a_lo, a_hi;
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Packet4f a_r128;
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a_lo = vget_low_f32(a.v);
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a_hi = vget_high_f32(a.v);
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a_r128 = vcombine_f32(a_hi, a_lo);
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return Packet2cf(a_r128);
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}
|
|
|
|
|
|
2011-02-23 17:51:40 +03:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet2cf pcplxflip<Packet2cf>(const Packet2cf& a)
|
2010-07-20 14:24:01 +02:00
|
|
|
{
|
|
|
|
|
return Packet2cf(vrev64q_f32(a.v));
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet2cf>(const Packet2cf& a)
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
float32x2_t a1, a2;
|
|
|
|
|
std::complex<float> s;
|
|
|
|
|
|
|
|
|
|
a1 = vget_low_f32(a.v);
|
|
|
|
|
a2 = vget_high_f32(a.v);
|
|
|
|
|
a2 = vadd_f32(a1, a2);
|
|
|
|
|
vst1_f32((float *)&s, a2);
|
|
|
|
|
|
|
|
|
|
return s;
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet2cf preduxp<Packet2cf>(const Packet2cf* vecs)
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
Packet4f sum1, sum2, sum;
|
|
|
|
|
|
|
|
|
|
// Add the first two 64-bit float32x2_t of vecs[0]
|
|
|
|
|
sum1 = vcombine_f32(vget_low_f32(vecs[0].v), vget_low_f32(vecs[1].v));
|
|
|
|
|
sum2 = vcombine_f32(vget_high_f32(vecs[0].v), vget_high_f32(vecs[1].v));
|
|
|
|
|
sum = vaddq_f32(sum1, sum2);
|
|
|
|
|
|
|
|
|
|
return Packet2cf(sum);
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet2cf>(const Packet2cf& a)
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
float32x2_t a1, a2, v1, v2, prod;
|
|
|
|
|
std::complex<float> s;
|
|
|
|
|
|
|
|
|
|
a1 = vget_low_f32(a.v);
|
|
|
|
|
a2 = vget_high_f32(a.v);
|
|
|
|
|
// Get the real values of a | a1_re | a1_re | a2_re | a2_re |
|
|
|
|
|
v1 = vdup_lane_f32(a1, 0);
|
|
|
|
|
// Get the real values of a | a1_im | a1_im | a2_im | a2_im |
|
|
|
|
|
v2 = vdup_lane_f32(a1, 1);
|
|
|
|
|
// Multiply the real a with b
|
|
|
|
|
v1 = vmul_f32(v1, a2);
|
|
|
|
|
// Multiply the imag a with b
|
|
|
|
|
v2 = vmul_f32(v2, a2);
|
|
|
|
|
// Conjugate v2
|
2016-06-28 11:12:49 -04:00
|
|
|
v2 = vreinterpret_f32_u32(veor_u32(vreinterpret_u32_f32(v2), p2ui_CONJ_XOR()));
|
2010-07-10 00:09:29 +03:00
|
|
|
// Swap real/imag elements in v2.
|
|
|
|
|
v2 = vrev64_f32(v2);
|
|
|
|
|
// Add v1, v2
|
|
|
|
|
prod = vadd_f32(v1, v2);
|
|
|
|
|
|
|
|
|
|
vst1_f32((float *)&s, prod);
|
|
|
|
|
|
|
|
|
|
return s;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<int Offset>
|
2010-10-25 10:15:22 -04:00
|
|
|
struct palign_impl<Offset,Packet2cf>
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE static void run(Packet2cf& first, const Packet2cf& second)
|
|
|
|
|
{
|
|
|
|
|
if (Offset==1)
|
|
|
|
|
{
|
|
|
|
|
first.v = vextq_f32(first.v, second.v, 2);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> struct conj_helper<Packet2cf, Packet2cf, false,true>
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const
|
2010-10-25 10:15:22 -04:00
|
|
|
{ return padd(pmul(x,y),c); }
|
2010-07-10 00:09:29 +03:00
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const
|
|
|
|
|
{
|
2011-02-23 09:41:55 +01:00
|
|
|
return internal::pmul(a, pconj(b));
|
2010-07-10 00:09:29 +03:00
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> struct conj_helper<Packet2cf, Packet2cf, true,false>
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const
|
2010-10-25 10:15:22 -04:00
|
|
|
{ return padd(pmul(x,y),c); }
|
2010-07-10 00:09:29 +03:00
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const
|
|
|
|
|
{
|
2011-02-23 09:41:55 +01:00
|
|
|
return internal::pmul(pconj(a), b);
|
2010-07-10 00:09:29 +03:00
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> struct conj_helper<Packet2cf, Packet2cf, true,true>
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const
|
2010-10-25 10:15:22 -04:00
|
|
|
{ return padd(pmul(x,y),c); }
|
2010-07-10 00:09:29 +03:00
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const
|
|
|
|
|
{
|
2011-02-23 09:41:55 +01:00
|
|
|
return pconj(internal::pmul(a, b));
|
2010-07-10 00:09:29 +03:00
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 10:16:30 +02:00
|
|
|
EIGEN_MAKE_CONJ_HELPER_CPLX_REAL(Packet2cf,Packet4f)
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet2cf pdiv<Packet2cf>(const Packet2cf& a, const Packet2cf& b)
|
2010-07-10 00:09:29 +03:00
|
|
|
{
|
2014-10-22 07:39:49 +00:00
|
|
|
// TODO optimize it for NEON
|
2010-10-25 10:15:22 -04:00
|
|
|
Packet2cf res = conj_helper<Packet2cf,Packet2cf,false,true>().pmul(a,b);
|
2010-07-10 00:09:29 +03:00
|
|
|
Packet4f s, rev_s;
|
|
|
|
|
|
|
|
|
|
// this computes the norm
|
|
|
|
|
s = vmulq_f32(b.v, b.v);
|
2013-06-10 15:59:03 +02:00
|
|
|
rev_s = vrev64q_f32(s);
|
2010-07-10 00:09:29 +03:00
|
|
|
|
2018-04-26 10:50:41 +02:00
|
|
|
return Packet2cf(pdiv<Packet4f>(res.v, vaddq_f32(s,rev_s)));
|
2010-07-10 00:09:29 +03:00
|
|
|
}
|
|
|
|
|
|
2014-04-25 11:15:13 +02:00
|
|
|
EIGEN_DEVICE_FUNC inline void
|
2014-04-25 10:56:18 +02:00
|
|
|
ptranspose(PacketBlock<Packet2cf,2>& kernel) {
|
2014-10-22 07:39:49 +00:00
|
|
|
Packet4f tmp = vcombine_f32(vget_high_f32(kernel.packet[0].v), vget_high_f32(kernel.packet[1].v));
|
2014-04-23 18:22:10 -07:00
|
|
|
kernel.packet[0].v = vcombine_f32(vget_low_f32(kernel.packet[0].v), vget_low_f32(kernel.packet[1].v));
|
|
|
|
|
kernel.packet[1].v = tmp;
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-22 07:39:49 +00:00
|
|
|
//---------- double ----------
|
2015-03-03 10:17:05 -05:00
|
|
|
#if EIGEN_ARCH_ARM64 && !EIGEN_APPLE_DOUBLE_NEON_BUG
|
2014-10-22 07:39:49 +00:00
|
|
|
|
2016-10-12 16:55:47 +02:00
|
|
|
// See bug 1325, clang fails to call vld1q_u64.
|
|
|
|
|
#if EIGEN_COMP_CLANG
|
|
|
|
|
static uint64x2_t p2ul_CONJ_XOR = {0x0, 0x8000000000000000};
|
|
|
|
|
#else
|
|
|
|
|
const uint64_t p2ul_conj_XOR_DATA[] = { 0x0, 0x8000000000000000 };
|
|
|
|
|
static uint64x2_t p2ul_CONJ_XOR = vld1q_u64( p2ul_conj_XOR_DATA );
|
|
|
|
|
#endif
|
2014-10-22 07:39:49 +00:00
|
|
|
|
|
|
|
|
struct Packet1cd
|
|
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd() {}
|
|
|
|
|
EIGEN_STRONG_INLINE explicit Packet1cd(const Packet2d& a) : v(a) {}
|
|
|
|
|
Packet2d v;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template<> struct packet_traits<std::complex<double> > : default_packet_traits
|
|
|
|
|
{
|
|
|
|
|
typedef Packet1cd type;
|
|
|
|
|
typedef Packet1cd half;
|
|
|
|
|
enum {
|
|
|
|
|
Vectorizable = 1,
|
|
|
|
|
AlignedOnScalar = 0,
|
|
|
|
|
size = 1,
|
|
|
|
|
HasHalfPacket = 0,
|
|
|
|
|
|
|
|
|
|
HasAdd = 1,
|
|
|
|
|
HasSub = 1,
|
|
|
|
|
HasMul = 1,
|
|
|
|
|
HasDiv = 1,
|
|
|
|
|
HasNegate = 1,
|
|
|
|
|
HasAbs = 0,
|
|
|
|
|
HasAbs2 = 0,
|
|
|
|
|
HasMin = 0,
|
|
|
|
|
HasMax = 0,
|
|
|
|
|
HasSetLinear = 0
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
|
|
|
template<> struct unpacket_traits<Packet1cd> { typedef std::complex<double> type; enum {size=1, alignment=Aligned16, vectorizable=true, masked_load_available=false}; typedef Packet1cd half; };
|
2014-10-22 07:39:49 +00:00
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pload<Packet1cd>(const std::complex<double>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet1cd(pload<Packet2d>((const double*)from)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd ploadu<Packet1cd>(const std::complex<double>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet1cd(ploadu<Packet2d>((const double*)from)); }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pset1<Packet1cd>(const std::complex<double>& from)
|
|
|
|
|
{ /* here we really have to use unaligned loads :( */ return ploadu<Packet1cd>(&from); }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd padd<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(padd<Packet2d>(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd psub<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(psub<Packet2d>(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pnegate(const Packet1cd& a) { return Packet1cd(pnegate<Packet2d>(a.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pconj(const Packet1cd& a) { return Packet1cd(vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a.v), p2ul_CONJ_XOR))); }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pmul<Packet1cd>(const Packet1cd& a, const Packet1cd& b)
|
|
|
|
|
{
|
|
|
|
|
Packet2d v1, v2;
|
|
|
|
|
|
|
|
|
|
// Get the real values of a
|
|
|
|
|
v1 = vdupq_lane_f64(vget_low_f64(a.v), 0);
|
2015-12-10 16:06:33 +01:00
|
|
|
// Get the imag values of a
|
|
|
|
|
v2 = vdupq_lane_f64(vget_high_f64(a.v), 0);
|
2014-10-22 07:39:49 +00:00
|
|
|
// Multiply the real a with b
|
|
|
|
|
v1 = vmulq_f64(v1, b.v);
|
|
|
|
|
// Multiply the imag a with b
|
|
|
|
|
v2 = vmulq_f64(v2, b.v);
|
|
|
|
|
// Conjugate v2
|
|
|
|
|
v2 = vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(v2), p2ul_CONJ_XOR));
|
|
|
|
|
// Swap real/imag elements in v2.
|
|
|
|
|
v2 = preverse<Packet2d>(v2);
|
|
|
|
|
// Add and return the result
|
|
|
|
|
return Packet1cd(vaddq_f64(v1, v2));
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-21 13:32:13 -08:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pcmp_eq(const Packet1cd& a, const Packet1cd& b)
|
|
|
|
|
{
|
|
|
|
|
// Compare real and imaginary parts of a and b to get the mask vector:
|
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|
// [re(a)==re(b), im(a)==im(b)]
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|
Packet2d eq = pcmp_eq<Packet2d>(a.v, b.v);
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// Swap real/imag elements in the mask in to get:
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|
// [im(a)==im(b), re(a)==re(b)]
|
2019-02-22 14:56:12 +01:00
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|
Packet2d eq_swapped = vreinterpretq_f64_u32(vrev64q_u32(vreinterpretq_u32_f64(eq)));
|
2019-02-21 13:32:13 -08:00
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// Return re(a)==re(b) & im(a)==im(b) by computing bitwise AND of eq and eq_swapped
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|
return Packet1cd(pand<Packet2d>(eq, eq_swapped));
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|
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|
}
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|
2014-10-22 07:39:49 +00:00
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template<> EIGEN_STRONG_INLINE Packet1cd pand <Packet1cd>(const Packet1cd& a, const Packet1cd& b)
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|
|
|
{
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return Packet1cd(vreinterpretq_f64_u64(vandq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));
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|
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|
}
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template<> EIGEN_STRONG_INLINE Packet1cd por <Packet1cd>(const Packet1cd& a, const Packet1cd& b)
|
|
|
|
|
{
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|
|
|
|
return Packet1cd(vreinterpretq_f64_u64(vorrq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));
|
|
|
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|
}
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template<> EIGEN_STRONG_INLINE Packet1cd pxor <Packet1cd>(const Packet1cd& a, const Packet1cd& b)
|
|
|
|
|
{
|
|
|
|
|
return Packet1cd(vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));
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|
|
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|
}
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template<> EIGEN_STRONG_INLINE Packet1cd pandnot<Packet1cd>(const Packet1cd& a, const Packet1cd& b)
|
|
|
|
|
{
|
|
|
|
|
return Packet1cd(vreinterpretq_f64_u64(vbicq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));
|
|
|
|
|
}
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template<> EIGEN_STRONG_INLINE Packet1cd ploaddup<Packet1cd>(const std::complex<double>* from) { return pset1<Packet1cd>(*from); }
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|
template<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> * to, const Packet1cd& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((double*)to, from.v); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> * to, const Packet1cd& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((double*)to, from.v); }
|
|
|
|
|
|
2018-04-18 18:46:34 +02:00
|
|
|
template<> EIGEN_STRONG_INLINE void prefetch<std::complex<double> >(const std::complex<double> * addr) { EIGEN_ARM_PREFETCH((const double *)addr); }
|
2014-10-22 07:39:49 +00:00
|
|
|
|
2015-02-16 15:05:41 +01:00
|
|
|
template<> EIGEN_DEVICE_FUNC inline Packet1cd pgather<std::complex<double>, Packet1cd>(const std::complex<double>* from, Index stride)
|
2014-10-22 07:39:49 +00:00
|
|
|
{
|
2015-05-15 11:15:53 -04:00
|
|
|
Packet2d res = pset1<Packet2d>(0.0);
|
2014-10-22 07:39:49 +00:00
|
|
|
res = vsetq_lane_f64(std::real(from[0*stride]), res, 0);
|
|
|
|
|
res = vsetq_lane_f64(std::imag(from[0*stride]), res, 1);
|
|
|
|
|
return Packet1cd(res);
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-16 15:05:41 +01:00
|
|
|
template<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<double>, Packet1cd>(std::complex<double>* to, const Packet1cd& from, Index stride)
|
2014-10-22 07:39:49 +00:00
|
|
|
{
|
|
|
|
|
to[stride*0] = std::complex<double>(vgetq_lane_f64(from.v, 0), vgetq_lane_f64(from.v, 1));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<double> pfirst<Packet1cd>(const Packet1cd& a)
|
|
|
|
|
{
|
2019-01-14 21:45:56 +01:00
|
|
|
EIGEN_ALIGN16 std::complex<double> res;
|
2014-10-22 07:39:49 +00:00
|
|
|
pstore<std::complex<double> >(&res, a);
|
|
|
|
|
|
|
|
|
|
return res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd preverse(const Packet1cd& a) { return a; }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet1cd>(const Packet1cd& a) { return pfirst(a); }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd preduxp<Packet1cd>(const Packet1cd* vecs) { return vecs[0]; }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet1cd>(const Packet1cd& a) { return pfirst(a); }
|
|
|
|
|
|
|
|
|
|
template<int Offset>
|
|
|
|
|
struct palign_impl<Offset,Packet1cd>
|
|
|
|
|
{
|
|
|
|
|
static EIGEN_STRONG_INLINE void run(Packet1cd& /*first*/, const Packet1cd& /*second*/)
|
|
|
|
|
{
|
|
|
|
|
// FIXME is it sure we never have to align a Packet1cd?
|
|
|
|
|
// Even though a std::complex<double> has 16 bytes, it is not necessarily aligned on a 16 bytes boundary...
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template<> struct conj_helper<Packet1cd, Packet1cd, false,true>
|
|
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const
|
|
|
|
|
{ return padd(pmul(x,y),c); }
|
|
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const
|
|
|
|
|
{
|
|
|
|
|
return internal::pmul(a, pconj(b));
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template<> struct conj_helper<Packet1cd, Packet1cd, true,false>
|
|
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const
|
|
|
|
|
{ return padd(pmul(x,y),c); }
|
|
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const
|
|
|
|
|
{
|
|
|
|
|
return internal::pmul(pconj(a), b);
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template<> struct conj_helper<Packet1cd, Packet1cd, true,true>
|
|
|
|
|
{
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const
|
|
|
|
|
{ return padd(pmul(x,y),c); }
|
|
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const
|
|
|
|
|
{
|
|
|
|
|
return pconj(internal::pmul(a, b));
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 10:16:30 +02:00
|
|
|
EIGEN_MAKE_CONJ_HELPER_CPLX_REAL(Packet1cd,Packet2d)
|
|
|
|
|
|
2014-10-22 07:39:49 +00:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet1cd pdiv<Packet1cd>(const Packet1cd& a, const Packet1cd& b)
|
|
|
|
|
{
|
|
|
|
|
// TODO optimize it for NEON
|
|
|
|
|
Packet1cd res = conj_helper<Packet1cd,Packet1cd,false,true>().pmul(a,b);
|
|
|
|
|
Packet2d s = pmul<Packet2d>(b.v, b.v);
|
|
|
|
|
Packet2d rev_s = preverse<Packet2d>(s);
|
|
|
|
|
|
|
|
|
|
return Packet1cd(pdiv(res.v, padd<Packet2d>(s,rev_s)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE Packet1cd pcplxflip/*<Packet1cd>*/(const Packet1cd& x)
|
|
|
|
|
{
|
|
|
|
|
return Packet1cd(preverse(Packet2d(x.v)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet1cd,2>& kernel)
|
|
|
|
|
{
|
|
|
|
|
Packet2d tmp = vcombine_f64(vget_high_f64(kernel.packet[0].v), vget_high_f64(kernel.packet[1].v));
|
|
|
|
|
kernel.packet[0].v = vcombine_f64(vget_low_f64(kernel.packet[0].v), vget_low_f64(kernel.packet[1].v));
|
|
|
|
|
kernel.packet[1].v = tmp;
|
|
|
|
|
}
|
2014-11-04 21:58:52 +01:00
|
|
|
#endif // EIGEN_ARCH_ARM64
|
2014-04-23 18:22:10 -07:00
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
} // end namespace internal
|
|
|
|
|
|
2012-04-15 11:06:28 +01:00
|
|
|
} // end namespace Eigen
|
|
|
|
|
|
2010-10-25 10:15:22 -04:00
|
|
|
#endif // EIGEN_COMPLEX_NEON_H
|