2014-04-28 10:32:27 -07:00
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// This file is part of Eigen, a lightweight C++ template library
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// for linear algebra.
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//
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// Copyright (C) 2014 Benoit Steiner <benoit.steiner.goog@gmail.com>
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//
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// This Source Code Form is subject to the terms of the Mozilla
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// Public License v. 2.0. If a copy of the MPL was not distributed
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// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
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#ifndef EIGEN_CXX11_TENSOR_TENSOR_EVALUATOR_H
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#define EIGEN_CXX11_TENSOR_TENSOR_EVALUATOR_H
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2023-08-21 16:25:22 +00:00
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// IWYU pragma: private
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2021-09-10 19:12:26 +00:00
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#include "./InternalHeaderCheck.h"
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2014-04-28 10:32:27 -07:00
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namespace Eigen {
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2025-02-05 17:36:00 +00:00
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// Generic evaluator
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/**
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2014-04-28 10:32:27 -07:00
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* \ingroup CXX11_Tensor_Module
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*
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2025-02-05 17:36:00 +00:00
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* \brief The tensor evaluator class.
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2014-04-28 10:32:27 -07:00
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*
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* These classes are responsible for the evaluation of the tensor expression.
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*
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* TODO: add support for more types of expressions, in particular expressions
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* leading to lvalues (slicing, reshaping, etc...)
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*/
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2014-06-10 09:14:44 -07:00
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template <typename Derived, typename Device>
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2014-04-28 10:32:27 -07:00
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struct TensorEvaluator {
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typedef typename Derived::Index Index;
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typedef typename Derived::Scalar Scalar;
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2014-05-16 15:08:05 -07:00
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typedef typename Derived::Scalar CoeffReturnType;
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2016-03-08 12:07:33 -08:00
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typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
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2014-06-04 09:21:48 -07:00
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typedef typename Derived::Dimensions Dimensions;
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2016-12-14 15:30:37 +00:00
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typedef Derived XprType;
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2022-04-04 17:33:33 +00:00
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static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
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2019-06-28 10:08:23 +01:00
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typedef typename internal::traits<Derived>::template MakePointer<Scalar>::Type TensorPointerType;
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typedef StorageMemory<Scalar, Device> Storage;
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typedef typename Storage::Type EvaluatorPointerType;
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2014-05-16 15:08:05 -07:00
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2015-01-14 12:47:46 -08:00
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// NumDimensions is -1 for variable dim tensors
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2022-04-04 17:33:33 +00:00
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static constexpr int NumCoords =
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internal::traits<Derived>::NumDimensions > 0 ? internal::traits<Derived>::NumDimensions : 0;
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2022-03-16 16:43:40 +00:00
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static constexpr int Layout = Derived::Layout;
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2015-01-14 12:47:46 -08:00
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2014-05-16 15:08:05 -07:00
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enum {
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2019-09-24 12:52:45 -07:00
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IsAligned = Derived::IsAligned,
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PacketAccess = (PacketType<CoeffReturnType, Device>::size > 1),
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2022-03-16 16:43:40 +00:00
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BlockAccess = internal::is_arithmetic<std::remove_const_t<Scalar>>::value,
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2019-09-24 12:52:45 -07:00
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PreferBlockAccess = false,
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CoordAccess = NumCoords > 0,
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RawAccess = true
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2014-05-16 15:08:05 -07:00
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};
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2014-04-28 10:32:27 -07:00
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2022-03-16 16:43:40 +00:00
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typedef std::remove_const_t<Scalar> ScalarNoConst;
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2019-10-09 12:45:31 -07:00
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2019-09-24 12:52:45 -07:00
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//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
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typedef internal::TensorBlockDescriptor<NumCoords, Index> TensorBlockDesc;
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2019-10-09 12:45:31 -07:00
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typedef internal::TensorBlockScratchAllocator<Device> TensorBlockScratch;
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typedef typename internal::TensorMaterializedBlock<ScalarNoConst, NumCoords, Layout, Index> TensorBlock;
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2019-09-24 12:52:45 -07:00
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//===--------------------------------------------------------------------===//
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2023-02-03 19:18:45 +00:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorEvaluator(const Derived& m, const Device& device)
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2019-09-24 12:52:45 -07:00
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: m_data(device.get((const_cast<TensorPointerType>(m.data())))), m_dims(m.dimensions()), m_device(device) {}
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2019-06-28 10:08:23 +01:00
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2014-06-13 09:56:51 -07:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Dimensions& dimensions() const { return m_dims; }
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2014-06-04 09:21:48 -07:00
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2021-05-11 22:47:49 +00:00
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EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType dest) {
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2022-03-16 16:43:40 +00:00
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if (!NumTraits<std::remove_const_t<Scalar>>::RequireInitialization && dest) {
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2019-06-28 10:08:23 +01:00
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m_device.memcpy((void*)(m_device.get(dest)), m_device.get(m_data), m_dims.TotalSize() * sizeof(Scalar));
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2014-08-13 08:26:44 -07:00
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return false;
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}
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return true;
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}
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2019-08-30 15:13:38 -07:00
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#ifdef EIGEN_USE_THREADS
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template <typename EvalSubExprsCallback>
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EIGEN_STRONG_INLINE void evalSubExprsIfNeededAsync(EvaluatorPointerType dest, EvalSubExprsCallback done) {
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2026-02-22 22:04:23 -08:00
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// TODO(ezhulenev): ThreadPoolDevice memcpy is a blocking operation.
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2019-08-30 15:13:38 -07:00
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done(evalSubExprsIfNeeded(dest));
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}
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#endif // EIGEN_USE_THREADS
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2021-05-11 22:47:49 +00:00
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EIGEN_STRONG_INLINE void cleanup() {}
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2014-06-13 09:56:51 -07:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE CoeffReturnType coeff(Index index) const {
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2019-06-28 10:08:23 +01:00
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eigen_assert(m_data != NULL);
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2014-04-28 10:32:27 -07:00
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return m_data[index];
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}
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2023-01-16 07:04:08 +00:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE CoeffReturnType& coeffRef(Index index) const {
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2019-06-28 10:08:23 +01:00
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eigen_assert(m_data != NULL);
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2014-04-28 10:32:27 -07:00
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return m_data[index];
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}
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2014-10-13 17:02:09 -07:00
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template <int LoadMode>
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2014-04-28 10:32:27 -07:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const {
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2016-03-08 12:07:33 -08:00
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return internal::ploadt<PacketReturnType, LoadMode>(m_data + index);
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2014-04-28 10:32:27 -07:00
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}
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Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
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// Return a packet starting at `index` where `umask` specifies which elements
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// have to be loaded. Type/size of mask depends on PacketReturnType, e.g. for
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// Packet16f, `umask` is of type uint16_t and if a bit is 1, corresponding
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// float element will be loaded, otherwise 0 will be loaded.
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// Function has been templatized to enable Sfinae.
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2019-05-07 18:30:44 +02:00
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template <typename PacketReturnTypeT>
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE
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2022-03-16 16:43:40 +00:00
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std::enable_if_t<internal::unpacket_traits<PacketReturnTypeT>::masked_load_available, PacketReturnTypeT>
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Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
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partialPacket(Index index, typename internal::unpacket_traits<PacketReturnTypeT>::mask_t umask) const {
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return internal::ploadu<PacketReturnTypeT>(m_data + index, umask);
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}
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2014-10-13 17:02:09 -07:00
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template <int StoreMode>
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2023-01-16 07:04:08 +00:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void writePacket(Index index, const PacketReturnType& x) const {
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2016-03-08 12:07:33 -08:00
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return internal::pstoret<Scalar, PacketReturnType, StoreMode>(m_data + index, x);
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2014-05-16 15:08:05 -07:00
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}
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2014-04-28 10:32:27 -07:00
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2015-01-14 12:47:46 -08:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE CoeffReturnType coeff(const array<DenseIndex, NumCoords>& coords) const {
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2019-06-28 10:08:23 +01:00
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eigen_assert(m_data != NULL);
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2015-02-10 12:25:02 -08:00
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if (static_cast<int>(Layout) == static_cast<int>(ColMajor)) {
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2015-01-14 12:47:46 -08:00
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return m_data[m_dims.IndexOfColMajor(coords)];
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} else {
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return m_data[m_dims.IndexOfRowMajor(coords)];
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}
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}
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2023-01-16 07:04:08 +00:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE CoeffReturnType& coeffRef(const array<DenseIndex, NumCoords>& coords) const {
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2019-06-28 10:08:23 +01:00
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eigen_assert(m_data != NULL);
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2015-02-10 12:13:19 -08:00
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if (static_cast<int>(Layout) == static_cast<int>(ColMajor)) {
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2015-01-14 12:47:46 -08:00
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return m_data[m_dims.IndexOfColMajor(coords)];
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} else {
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return m_data[m_dims.IndexOfRowMajor(coords)];
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}
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}
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2016-04-14 13:57:35 -07:00
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
return TensorOpCost(sizeof(CoeffReturnType), 0, 0, vectorized, PacketType<CoeffReturnType, Device>::size);
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE internal::TensorBlockResourceRequirements getResourceRequirements() const {
|
|
|
|
|
return internal::TensorBlockResourceRequirements::any();
|
2019-12-09 16:19:38 -08:00
|
|
|
}
|
2018-07-25 13:51:10 -07:00
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorBlock block(TensorBlockDesc& desc, TensorBlockScratch& scratch,
|
2019-10-14 14:31:59 -07:00
|
|
|
bool /*root_of_expr_ast*/ = false) const {
|
2022-10-04 17:11:23 +00:00
|
|
|
eigen_assert(m_data != NULL);
|
2019-12-10 15:40:23 -08:00
|
|
|
return TensorBlock::materialize(m_data, m_dims, desc, scratch);
|
2019-10-09 12:45:31 -07:00
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
template <typename TensorBlock>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void writeBlock(const TensorBlockDesc& desc, const TensorBlock& block) {
|
2022-10-04 17:11:23 +00:00
|
|
|
eigen_assert(m_data != NULL);
|
2019-09-24 12:52:45 -07:00
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
typedef typename TensorBlock::XprType TensorBlockExpr;
|
2019-09-24 12:52:45 -07:00
|
|
|
typedef internal::TensorBlockAssignment<Scalar, NumCoords, TensorBlockExpr, Index> TensorBlockAssign;
|
|
|
|
|
|
2019-10-02 12:44:06 -07:00
|
|
|
TensorBlockAssign::Run(
|
|
|
|
|
TensorBlockAssign::target(desc.dimensions(), internal::strides<Layout>(m_dims), m_data, desc.offset()),
|
|
|
|
|
block.expr());
|
2019-09-24 12:52:45 -07:00
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EvaluatorPointerType data() const { return m_data; }
|
2014-08-13 08:26:44 -07:00
|
|
|
|
2014-04-28 10:32:27 -07:00
|
|
|
protected:
|
2019-06-28 10:08:23 +01:00
|
|
|
EvaluatorPointerType m_data;
|
2014-06-04 09:21:48 -07:00
|
|
|
Dimensions m_dims;
|
2019-08-02 11:18:13 -07:00
|
|
|
const Device EIGEN_DEVICE_REF m_device;
|
2014-04-28 10:32:27 -07:00
|
|
|
};
|
|
|
|
|
|
2022-02-04 19:01:07 +00:00
|
|
|
namespace internal {
|
2015-07-06 13:32:38 -07:00
|
|
|
template <typename T>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE T loadConstant(const T* address) {
|
|
|
|
|
return *address;
|
|
|
|
|
}
|
|
|
|
|
// Use the texture cache on CUDA devices whenever possible
|
2026-04-09 13:38:04 -07:00
|
|
|
#if defined(EIGEN_CUDA_ARCH)
|
2015-07-06 13:32:38 -07:00
|
|
|
template <>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE float loadConstant(const float* address) {
|
|
|
|
|
return __ldg(address);
|
|
|
|
|
}
|
|
|
|
|
template <>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE double loadConstant(const double* address) {
|
|
|
|
|
return __ldg(address);
|
|
|
|
|
}
|
2016-05-11 21:26:48 -07:00
|
|
|
template <>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Eigen::half loadConstant(const Eigen::half* address) {
|
2016-07-29 13:45:56 -07:00
|
|
|
return Eigen::half(half_impl::raw_uint16_to_half(__ldg(&address->x)));
|
2016-05-11 21:26:48 -07:00
|
|
|
}
|
2015-07-06 13:32:38 -07:00
|
|
|
#endif
|
2023-05-05 17:30:36 +00:00
|
|
|
|
2022-02-04 19:01:07 +00:00
|
|
|
} // namespace internal
|
2014-04-28 10:32:27 -07:00
|
|
|
|
2014-07-08 16:43:28 -07:00
|
|
|
// Default evaluator for rvalues
|
|
|
|
|
template <typename Derived, typename Device>
|
|
|
|
|
struct TensorEvaluator<const Derived, Device> {
|
|
|
|
|
typedef typename Derived::Index Index;
|
|
|
|
|
typedef typename Derived::Scalar Scalar;
|
|
|
|
|
typedef typename Derived::Scalar CoeffReturnType;
|
2016-03-08 12:07:33 -08:00
|
|
|
typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
|
2014-07-08 16:43:28 -07:00
|
|
|
typedef typename Derived::Dimensions Dimensions;
|
2016-12-14 15:30:37 +00:00
|
|
|
typedef const Derived XprType;
|
2019-06-28 10:08:23 +01:00
|
|
|
typedef typename internal::traits<Derived>::template MakePointer<const Scalar>::Type TensorPointerType;
|
|
|
|
|
typedef StorageMemory<const Scalar, Device> Storage;
|
|
|
|
|
typedef typename Storage::Type EvaluatorPointerType;
|
2014-07-08 16:43:28 -07:00
|
|
|
|
2022-03-16 16:43:40 +00:00
|
|
|
typedef std::remove_const_t<Scalar> ScalarNoConst;
|
2019-09-24 12:52:45 -07:00
|
|
|
|
2015-01-14 12:47:46 -08:00
|
|
|
// NumDimensions is -1 for variable dim tensors
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int NumCoords =
|
|
|
|
|
internal::traits<Derived>::NumDimensions > 0 ? internal::traits<Derived>::NumDimensions : 0;
|
|
|
|
|
static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
|
2022-03-16 16:43:40 +00:00
|
|
|
static constexpr int Layout = Derived::Layout;
|
2015-01-14 12:47:46 -08:00
|
|
|
|
2014-07-08 16:43:28 -07:00
|
|
|
enum {
|
2019-09-24 12:52:45 -07:00
|
|
|
IsAligned = Derived::IsAligned,
|
|
|
|
|
PacketAccess = (PacketType<CoeffReturnType, Device>::size > 1),
|
2019-12-10 15:40:23 -08:00
|
|
|
BlockAccess = internal::is_arithmetic<ScalarNoConst>::value,
|
2018-08-10 16:53:36 -07:00
|
|
|
PreferBlockAccess = false,
|
2019-09-24 12:52:45 -07:00
|
|
|
CoordAccess = NumCoords > 0,
|
|
|
|
|
RawAccess = true
|
2014-07-08 16:43:28 -07:00
|
|
|
};
|
|
|
|
|
|
2019-09-24 12:52:45 -07:00
|
|
|
//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
|
|
|
|
|
typedef internal::TensorBlockDescriptor<NumCoords, Index> TensorBlockDesc;
|
|
|
|
|
typedef internal::TensorBlockScratchAllocator<Device> TensorBlockScratch;
|
|
|
|
|
|
|
|
|
|
typedef typename internal::TensorMaterializedBlock<ScalarNoConst, NumCoords, Layout, Index> TensorBlock;
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
2023-02-03 19:18:45 +00:00
|
|
|
EIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC TensorEvaluator(const Derived& m, const Device& device)
|
2019-06-28 10:08:23 +01:00
|
|
|
: m_data(device.get(m.data())), m_dims(m.dimensions()), m_device(device) {}
|
2014-07-08 16:43:28 -07:00
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Dimensions& dimensions() const { return m_dims; }
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType data) {
|
2022-03-16 16:43:40 +00:00
|
|
|
if (!NumTraits<std::remove_const_t<Scalar>>::RequireInitialization && data) {
|
2019-06-28 10:08:23 +01:00
|
|
|
m_device.memcpy((void*)(m_device.get(data)), m_device.get(m_data), m_dims.TotalSize() * sizeof(Scalar));
|
2015-04-20 17:34:11 -07:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-30 15:13:38 -07:00
|
|
|
#ifdef EIGEN_USE_THREADS
|
|
|
|
|
template <typename EvalSubExprsCallback>
|
|
|
|
|
EIGEN_STRONG_INLINE void evalSubExprsIfNeededAsync(EvaluatorPointerType dest, EvalSubExprsCallback done) {
|
2026-02-22 22:04:23 -08:00
|
|
|
// TODO(ezhulenev): ThreadPoolDevice memcpy is a blocking operation.
|
2019-08-30 15:13:38 -07:00
|
|
|
done(evalSubExprsIfNeeded(dest));
|
|
|
|
|
}
|
|
|
|
|
#endif // EIGEN_USE_THREADS
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE void cleanup() {}
|
2014-07-08 16:43:28 -07:00
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE CoeffReturnType coeff(Index index) const {
|
2019-06-28 10:08:23 +01:00
|
|
|
eigen_assert(m_data != NULL);
|
2022-02-04 19:01:07 +00:00
|
|
|
return internal::loadConstant(m_data + index);
|
2014-07-08 16:43:28 -07:00
|
|
|
}
|
|
|
|
|
|
2014-10-13 17:02:09 -07:00
|
|
|
template <int LoadMode>
|
2014-07-08 16:43:28 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const {
|
2016-03-08 12:07:33 -08:00
|
|
|
return internal::ploadt_ro<PacketReturnType, LoadMode>(m_data + index);
|
2014-07-08 16:43:28 -07:00
|
|
|
}
|
|
|
|
|
|
Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
|
|
|
// Return a packet starting at `index` where `umask` specifies which elements
|
|
|
|
|
// have to be loaded. Type/size of mask depends on PacketReturnType, e.g. for
|
|
|
|
|
// Packet16f, `umask` is of type uint16_t and if a bit is 1, corresponding
|
|
|
|
|
// float element will be loaded, otherwise 0 will be loaded.
|
|
|
|
|
// Function has been templatized to enable Sfinae.
|
2019-05-07 18:30:44 +02:00
|
|
|
template <typename PacketReturnTypeT>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE
|
2022-03-16 16:43:40 +00:00
|
|
|
std::enable_if_t<internal::unpacket_traits<PacketReturnTypeT>::masked_load_available, PacketReturnTypeT>
|
Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
|
|
|
partialPacket(Index index, typename internal::unpacket_traits<PacketReturnTypeT>::mask_t umask) const {
|
|
|
|
|
return internal::ploadu<PacketReturnTypeT>(m_data + index, umask);
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-14 12:47:46 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE CoeffReturnType coeff(const array<DenseIndex, NumCoords>& coords) const {
|
2019-06-28 10:08:23 +01:00
|
|
|
eigen_assert(m_data != NULL);
|
2015-02-10 12:25:02 -08:00
|
|
|
const Index index = (static_cast<int>(Layout) == static_cast<int>(ColMajor)) ? m_dims.IndexOfColMajor(coords)
|
2015-01-14 12:47:46 -08:00
|
|
|
: m_dims.IndexOfRowMajor(coords);
|
2022-02-04 19:01:07 +00:00
|
|
|
return internal::loadConstant(m_data + index);
|
2015-01-14 12:47:46 -08:00
|
|
|
}
|
|
|
|
|
|
2016-04-14 18:28:23 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
return TensorOpCost(sizeof(CoeffReturnType), 0, 0, vectorized, PacketType<CoeffReturnType, Device>::size);
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE internal::TensorBlockResourceRequirements getResourceRequirements() const {
|
|
|
|
|
return internal::TensorBlockResourceRequirements::any();
|
2019-12-09 16:19:38 -08:00
|
|
|
}
|
2018-07-25 13:51:10 -07:00
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorBlock block(TensorBlockDesc& desc, TensorBlockScratch& scratch,
|
2019-10-14 14:31:59 -07:00
|
|
|
bool /*root_of_expr_ast*/ = false) const {
|
2022-10-04 17:11:23 +00:00
|
|
|
eigen_assert(m_data != NULL);
|
2019-12-10 15:40:23 -08:00
|
|
|
return TensorBlock::materialize(m_data, m_dims, desc, scratch);
|
2019-09-24 12:52:45 -07:00
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EvaluatorPointerType data() const { return m_data; }
|
2023-05-05 17:30:36 +00:00
|
|
|
|
2014-07-08 16:43:28 -07:00
|
|
|
protected:
|
2019-06-28 10:08:23 +01:00
|
|
|
EvaluatorPointerType m_data;
|
2014-07-08 16:43:28 -07:00
|
|
|
Dimensions m_dims;
|
2019-08-02 11:18:13 -07:00
|
|
|
const Device EIGEN_DEVICE_REF m_device;
|
2014-07-08 16:43:28 -07:00
|
|
|
};
|
|
|
|
|
|
2014-05-22 16:22:35 -07:00
|
|
|
// -------------------- CwiseNullaryOp --------------------
|
|
|
|
|
|
2014-06-10 09:14:44 -07:00
|
|
|
template <typename NullaryOp, typename ArgType, typename Device>
|
|
|
|
|
struct TensorEvaluator<const TensorCwiseNullaryOp<NullaryOp, ArgType>, Device> {
|
2014-06-04 09:21:48 -07:00
|
|
|
typedef TensorCwiseNullaryOp<NullaryOp, ArgType> XprType;
|
2014-05-22 16:22:35 -07:00
|
|
|
|
2014-06-10 09:14:44 -07:00
|
|
|
EIGEN_DEVICE_FUNC TensorEvaluator(const XprType& op, const Device& device)
|
2016-09-01 13:40:45 +02:00
|
|
|
: m_functor(op.functor()), m_argImpl(op.nestedExpression(), device), m_wrapper() {}
|
2014-05-22 16:22:35 -07:00
|
|
|
|
|
|
|
|
typedef typename XprType::Index Index;
|
2014-08-13 08:26:44 -07:00
|
|
|
typedef typename XprType::Scalar Scalar;
|
2014-10-16 10:41:07 -07:00
|
|
|
typedef typename internal::traits<XprType>::Scalar CoeffReturnType;
|
2016-03-08 12:07:33 -08:00
|
|
|
typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
|
2014-06-10 09:14:44 -07:00
|
|
|
typedef typename TensorEvaluator<ArgType, Device>::Dimensions Dimensions;
|
2019-06-28 10:08:23 +01:00
|
|
|
typedef StorageMemory<CoeffReturnType, Device> Storage;
|
|
|
|
|
typedef typename Storage::Type EvaluatorPointerType;
|
|
|
|
|
|
2022-03-16 16:43:40 +00:00
|
|
|
static constexpr int Layout = TensorEvaluator<ArgType, Device>::Layout;
|
2019-06-28 10:08:23 +01:00
|
|
|
enum {
|
|
|
|
|
IsAligned = true,
|
|
|
|
|
PacketAccess = internal::functor_traits<NullaryOp>::PacketAccess
|
|
|
|
|
#ifdef EIGEN_USE_SYCL
|
|
|
|
|
&& (PacketType<CoeffReturnType, Device>::size > 1)
|
|
|
|
|
#endif
|
|
|
|
|
,
|
2019-12-10 15:40:23 -08:00
|
|
|
BlockAccess = false,
|
2019-06-28 10:08:23 +01:00
|
|
|
PreferBlockAccess = false,
|
|
|
|
|
CoordAccess = false, // to be implemented
|
|
|
|
|
RawAccess = false
|
|
|
|
|
};
|
2014-06-04 09:21:48 -07:00
|
|
|
|
2019-09-24 12:52:45 -07:00
|
|
|
//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
|
2019-12-10 15:40:23 -08:00
|
|
|
typedef internal::TensorBlockNotImplemented TensorBlock;
|
2019-09-24 12:52:45 -07:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
2014-06-04 09:21:48 -07:00
|
|
|
EIGEN_DEVICE_FUNC const Dimensions& dimensions() const { return m_argImpl.dimensions(); }
|
2014-05-22 16:22:35 -07:00
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType) { return true; }
|
2019-08-30 15:13:38 -07:00
|
|
|
|
|
|
|
|
#ifdef EIGEN_USE_THREADS
|
|
|
|
|
template <typename EvalSubExprsCallback>
|
|
|
|
|
EIGEN_STRONG_INLINE void evalSubExprsIfNeededAsync(EvaluatorPointerType, EvalSubExprsCallback done) {
|
|
|
|
|
done(true);
|
|
|
|
|
}
|
|
|
|
|
#endif // EIGEN_USE_THREADS
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE void cleanup() {}
|
2014-06-13 09:56:51 -07:00
|
|
|
|
2014-05-22 16:22:35 -07:00
|
|
|
EIGEN_DEVICE_FUNC CoeffReturnType coeff(Index index) const { return m_wrapper(m_functor, index); }
|
|
|
|
|
|
|
|
|
|
template <int LoadMode>
|
2014-10-13 17:02:09 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const {
|
2016-09-02 15:29:34 -07:00
|
|
|
return m_wrapper.template packetOp<PacketReturnType, Index>(m_functor, index);
|
2014-05-22 16:22:35 -07:00
|
|
|
}
|
|
|
|
|
|
2016-04-14 13:57:35 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
return TensorOpCost(sizeof(CoeffReturnType), 0, 0, vectorized, PacketType<CoeffReturnType, Device>::size);
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EvaluatorPointerType data() const { return NULL; }
|
2016-09-19 12:44:13 +01:00
|
|
|
|
2014-05-22 16:22:35 -07:00
|
|
|
private:
|
|
|
|
|
const NullaryOp m_functor;
|
2014-06-10 09:14:44 -07:00
|
|
|
TensorEvaluator<ArgType, Device> m_argImpl;
|
2016-09-01 13:40:45 +02:00
|
|
|
const internal::nullary_wrapper<CoeffReturnType, NullaryOp> m_wrapper;
|
2014-05-22 16:22:35 -07:00
|
|
|
};
|
|
|
|
|
|
2014-04-28 10:32:27 -07:00
|
|
|
// -------------------- CwiseUnaryOp --------------------
|
|
|
|
|
|
2014-06-10 09:14:44 -07:00
|
|
|
template <typename UnaryOp, typename ArgType, typename Device>
|
|
|
|
|
struct TensorEvaluator<const TensorCwiseUnaryOp<UnaryOp, ArgType>, Device> {
|
2014-04-28 10:32:27 -07:00
|
|
|
typedef TensorCwiseUnaryOp<UnaryOp, ArgType> XprType;
|
|
|
|
|
|
2022-03-16 16:43:40 +00:00
|
|
|
static constexpr int Layout = TensorEvaluator<ArgType, Device>::Layout;
|
2014-05-16 15:08:05 -07:00
|
|
|
enum {
|
2018-08-10 16:53:36 -07:00
|
|
|
IsAligned = TensorEvaluator<ArgType, Device>::IsAligned,
|
2021-06-15 09:09:31 -07:00
|
|
|
PacketAccess =
|
|
|
|
|
int(TensorEvaluator<ArgType, Device>::PacketAccess) & int(internal::functor_traits<UnaryOp>::PacketAccess),
|
2019-12-10 15:40:23 -08:00
|
|
|
BlockAccess = TensorEvaluator<ArgType, Device>::BlockAccess,
|
2018-08-10 16:53:36 -07:00
|
|
|
PreferBlockAccess = TensorEvaluator<ArgType, Device>::PreferBlockAccess,
|
|
|
|
|
CoordAccess = false, // to be implemented
|
|
|
|
|
RawAccess = false
|
2014-05-16 15:08:05 -07:00
|
|
|
};
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_DEVICE_FUNC TensorEvaluator(const XprType& op, const Device& device)
|
2014-06-10 09:14:44 -07:00
|
|
|
: m_device(device), m_functor(op.functor()), m_argImpl(op.nestedExpression(), device) {}
|
2014-04-28 10:32:27 -07:00
|
|
|
|
|
|
|
|
typedef typename XprType::Index Index;
|
2014-08-13 08:26:44 -07:00
|
|
|
typedef typename XprType::Scalar Scalar;
|
2022-03-16 16:43:40 +00:00
|
|
|
typedef std::remove_const_t<Scalar> ScalarNoConst;
|
2014-10-16 10:41:07 -07:00
|
|
|
typedef typename internal::traits<XprType>::Scalar CoeffReturnType;
|
2016-03-08 12:07:33 -08:00
|
|
|
typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
|
2014-06-10 09:14:44 -07:00
|
|
|
typedef typename TensorEvaluator<ArgType, Device>::Dimensions Dimensions;
|
2019-06-28 10:08:23 +01:00
|
|
|
typedef StorageMemory<CoeffReturnType, Device> Storage;
|
|
|
|
|
typedef typename Storage::Type EvaluatorPointerType;
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int NumDims = internal::array_size<Dimensions>::value;
|
2018-08-10 16:53:36 -07:00
|
|
|
|
2019-09-24 12:52:45 -07:00
|
|
|
//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
|
|
|
|
|
typedef internal::TensorBlockDescriptor<NumDims, Index> TensorBlockDesc;
|
|
|
|
|
typedef internal::TensorBlockScratchAllocator<Device> TensorBlockScratch;
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
typedef typename TensorEvaluator<const ArgType, Device>::TensorBlock ArgTensorBlock;
|
2019-09-24 12:52:45 -07:00
|
|
|
|
|
|
|
|
typedef internal::TensorCwiseUnaryBlock<UnaryOp, ArgTensorBlock> TensorBlock;
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
2014-06-04 09:21:48 -07:00
|
|
|
EIGEN_DEVICE_FUNC const Dimensions& dimensions() const { return m_argImpl.dimensions(); }
|
2014-04-28 10:32:27 -07:00
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType) {
|
2014-08-13 08:26:44 -07:00
|
|
|
m_argImpl.evalSubExprsIfNeeded(NULL);
|
|
|
|
|
return true;
|
2014-06-13 09:56:51 -07:00
|
|
|
}
|
2019-08-30 15:13:38 -07:00
|
|
|
|
|
|
|
|
#ifdef EIGEN_USE_THREADS
|
|
|
|
|
template <typename EvalSubExprsCallback>
|
|
|
|
|
EIGEN_STRONG_INLINE void evalSubExprsIfNeededAsync(EvaluatorPointerType, EvalSubExprsCallback done) {
|
|
|
|
|
m_argImpl.evalSubExprsIfNeededAsync(nullptr, [done](bool) { done(true); });
|
|
|
|
|
}
|
|
|
|
|
#endif // EIGEN_USE_THREADS
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE void cleanup() { m_argImpl.cleanup(); }
|
2014-06-13 09:56:51 -07:00
|
|
|
|
2014-05-16 15:08:05 -07:00
|
|
|
EIGEN_DEVICE_FUNC CoeffReturnType coeff(Index index) const { return m_functor(m_argImpl.coeff(index)); }
|
2014-04-28 10:32:27 -07:00
|
|
|
|
2014-05-16 15:08:05 -07:00
|
|
|
template <int LoadMode>
|
2014-10-13 17:02:09 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const {
|
2014-05-16 15:08:05 -07:00
|
|
|
return m_functor.packetOp(m_argImpl.template packet<LoadMode>(index));
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-14 13:57:35 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
const double functor_cost = internal::functor_traits<UnaryOp>::Cost;
|
|
|
|
|
return m_argImpl.costPerCoeff(vectorized) + TensorOpCost(0, 0, functor_cost, vectorized, PacketSize);
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE internal::TensorBlockResourceRequirements getResourceRequirements() const {
|
2026-04-01 17:49:56 -07:00
|
|
|
static constexpr double functor_cost = internal::functor_traits<UnaryOp>::Cost;
|
2019-12-18 20:07:00 +00:00
|
|
|
return m_argImpl.getResourceRequirements().addCostPerCoeff({0, 0, functor_cost / PacketSize});
|
2018-08-10 16:53:36 -07:00
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorBlock block(TensorBlockDesc& desc, TensorBlockScratch& scratch,
|
2019-10-14 14:31:59 -07:00
|
|
|
bool /*root_of_expr_ast*/ = false) const {
|
2019-12-10 15:40:23 -08:00
|
|
|
return TensorBlock(m_argImpl.block(desc, scratch), m_functor);
|
2019-09-24 12:52:45 -07:00
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EvaluatorPointerType data() const { return NULL; }
|
2014-08-13 08:26:44 -07:00
|
|
|
|
2014-04-28 10:32:27 -07:00
|
|
|
private:
|
2019-08-02 11:18:13 -07:00
|
|
|
const Device EIGEN_DEVICE_REF m_device;
|
2014-04-28 10:32:27 -07:00
|
|
|
const UnaryOp m_functor;
|
2014-06-10 09:14:44 -07:00
|
|
|
TensorEvaluator<ArgType, Device> m_argImpl;
|
2014-04-28 10:32:27 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// -------------------- CwiseBinaryOp --------------------
|
|
|
|
|
|
2014-06-10 09:14:44 -07:00
|
|
|
template <typename BinaryOp, typename LeftArgType, typename RightArgType, typename Device>
|
|
|
|
|
struct TensorEvaluator<const TensorCwiseBinaryOp<BinaryOp, LeftArgType, RightArgType>, Device> {
|
2014-04-28 10:32:27 -07:00
|
|
|
typedef TensorCwiseBinaryOp<BinaryOp, LeftArgType, RightArgType> XprType;
|
|
|
|
|
|
2022-03-16 16:43:40 +00:00
|
|
|
static constexpr int Layout = TensorEvaluator<LeftArgType, Device>::Layout;
|
2014-05-16 15:08:05 -07:00
|
|
|
enum {
|
2021-06-15 09:09:31 -07:00
|
|
|
IsAligned =
|
|
|
|
|
int(TensorEvaluator<LeftArgType, Device>::IsAligned) & int(TensorEvaluator<RightArgType, Device>::IsAligned),
|
|
|
|
|
PacketAccess = int(TensorEvaluator<LeftArgType, Device>::PacketAccess) &
|
|
|
|
|
int(TensorEvaluator<RightArgType, Device>::PacketAccess) &
|
|
|
|
|
int(internal::functor_traits<BinaryOp>::PacketAccess),
|
|
|
|
|
BlockAccess = int(TensorEvaluator<LeftArgType, Device>::BlockAccess) &
|
|
|
|
|
int(TensorEvaluator<RightArgType, Device>::BlockAccess),
|
|
|
|
|
PreferBlockAccess = int(TensorEvaluator<LeftArgType, Device>::PreferBlockAccess) |
|
|
|
|
|
int(TensorEvaluator<RightArgType, Device>::PreferBlockAccess),
|
2018-08-10 16:53:36 -07:00
|
|
|
CoordAccess = false, // to be implemented
|
|
|
|
|
RawAccess = false
|
2014-05-16 15:08:05 -07:00
|
|
|
};
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_DEVICE_FUNC TensorEvaluator(const XprType& op, const Device& device)
|
2018-07-25 13:51:10 -07:00
|
|
|
: m_device(device),
|
|
|
|
|
m_functor(op.functor()),
|
2014-06-10 09:14:44 -07:00
|
|
|
m_leftImpl(op.lhsExpression(), device),
|
|
|
|
|
m_rightImpl(op.rhsExpression(), device) {
|
2015-10-29 17:27:38 -07:00
|
|
|
EIGEN_STATIC_ASSERT((static_cast<int>(TensorEvaluator<LeftArgType, Device>::Layout) ==
|
|
|
|
|
static_cast<int>(TensorEvaluator<RightArgType, Device>::Layout) ||
|
|
|
|
|
internal::traits<XprType>::NumDimensions <= 1),
|
|
|
|
|
YOU_MADE_A_PROGRAMMING_MISTAKE);
|
2015-01-14 12:47:46 -08:00
|
|
|
eigen_assert(dimensions_match(m_leftImpl.dimensions(), m_rightImpl.dimensions()));
|
2014-11-04 10:24:42 -08:00
|
|
|
}
|
2014-04-28 10:32:27 -07:00
|
|
|
|
|
|
|
|
typedef typename XprType::Index Index;
|
2014-08-13 08:26:44 -07:00
|
|
|
typedef typename XprType::Scalar Scalar;
|
2014-10-16 10:41:07 -07:00
|
|
|
typedef typename internal::traits<XprType>::Scalar CoeffReturnType;
|
2016-03-08 12:07:33 -08:00
|
|
|
typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
|
2014-06-10 09:14:44 -07:00
|
|
|
typedef typename TensorEvaluator<LeftArgType, Device>::Dimensions Dimensions;
|
2019-06-28 10:08:23 +01:00
|
|
|
typedef StorageMemory<CoeffReturnType, Device> Storage;
|
|
|
|
|
typedef typename Storage::Type EvaluatorPointerType;
|
2014-06-04 09:21:48 -07:00
|
|
|
|
2018-07-25 13:51:10 -07:00
|
|
|
static constexpr int NumDims = internal::array_size<typename TensorEvaluator<LeftArgType, Device>::Dimensions>::value;
|
|
|
|
|
|
2019-09-24 12:52:45 -07:00
|
|
|
//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
|
|
|
|
|
typedef internal::TensorBlockDescriptor<NumDims, Index> TensorBlockDesc;
|
|
|
|
|
typedef internal::TensorBlockScratchAllocator<Device> TensorBlockScratch;
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
typedef typename TensorEvaluator<const LeftArgType, Device>::TensorBlock LeftTensorBlock;
|
|
|
|
|
typedef typename TensorEvaluator<const RightArgType, Device>::TensorBlock RightTensorBlock;
|
2019-09-24 12:52:45 -07:00
|
|
|
|
|
|
|
|
typedef internal::TensorCwiseBinaryBlock<BinaryOp, LeftTensorBlock, RightTensorBlock> TensorBlock;
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
2014-06-04 09:21:48 -07:00
|
|
|
EIGEN_DEVICE_FUNC const Dimensions& dimensions() const {
|
|
|
|
|
// TODO: use right impl instead if right impl dimensions are known at compile time.
|
|
|
|
|
return m_leftImpl.dimensions();
|
|
|
|
|
}
|
2014-04-28 10:32:27 -07:00
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType) {
|
2014-08-13 08:26:44 -07:00
|
|
|
m_leftImpl.evalSubExprsIfNeeded(NULL);
|
|
|
|
|
m_rightImpl.evalSubExprsIfNeeded(NULL);
|
|
|
|
|
return true;
|
2014-06-13 09:56:51 -07:00
|
|
|
}
|
2019-08-30 15:13:38 -07:00
|
|
|
|
|
|
|
|
#ifdef EIGEN_USE_THREADS
|
|
|
|
|
template <typename EvalSubExprsCallback>
|
|
|
|
|
EIGEN_STRONG_INLINE void evalSubExprsIfNeededAsync(EvaluatorPointerType, EvalSubExprsCallback done) {
|
|
|
|
|
// TODO(ezhulenev): Evaluate two expression in parallel?
|
|
|
|
|
m_leftImpl.evalSubExprsIfNeededAsync(
|
|
|
|
|
nullptr, [this, done](bool) { m_rightImpl.evalSubExprsIfNeededAsync(nullptr, [done](bool) { done(true); }); });
|
|
|
|
|
}
|
|
|
|
|
#endif // EIGEN_USE_THREADS
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE void cleanup() {
|
2014-06-13 09:56:51 -07:00
|
|
|
m_leftImpl.cleanup();
|
|
|
|
|
m_rightImpl.cleanup();
|
|
|
|
|
}
|
|
|
|
|
|
2014-05-16 15:08:05 -07:00
|
|
|
EIGEN_DEVICE_FUNC CoeffReturnType coeff(Index index) const {
|
2014-04-28 10:32:27 -07:00
|
|
|
return m_functor(m_leftImpl.coeff(index), m_rightImpl.coeff(index));
|
|
|
|
|
}
|
2014-05-16 15:08:05 -07:00
|
|
|
template <int LoadMode>
|
2014-10-13 17:02:09 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const {
|
2014-05-16 15:08:05 -07:00
|
|
|
return m_functor.packetOp(m_leftImpl.template packet<LoadMode>(index),
|
|
|
|
|
m_rightImpl.template packet<LoadMode>(index));
|
|
|
|
|
}
|
2014-04-28 10:32:27 -07:00
|
|
|
|
2016-04-14 13:57:35 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
const double functor_cost = internal::functor_traits<BinaryOp>::Cost;
|
|
|
|
|
return m_leftImpl.costPerCoeff(vectorized) + m_rightImpl.costPerCoeff(vectorized) +
|
|
|
|
|
TensorOpCost(0, 0, functor_cost, vectorized, PacketSize);
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE internal::TensorBlockResourceRequirements getResourceRequirements() const {
|
2026-04-01 17:49:56 -07:00
|
|
|
static constexpr double functor_cost = internal::functor_traits<BinaryOp>::Cost;
|
2019-12-10 15:40:23 -08:00
|
|
|
return internal::TensorBlockResourceRequirements::merge(m_leftImpl.getResourceRequirements(),
|
2019-12-18 20:07:00 +00:00
|
|
|
m_rightImpl.getResourceRequirements())
|
|
|
|
|
.addCostPerCoeff({0, 0, functor_cost / PacketSize});
|
2018-07-25 13:51:10 -07:00
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorBlock block(TensorBlockDesc& desc, TensorBlockScratch& scratch,
|
2019-10-14 14:31:59 -07:00
|
|
|
bool /*root_of_expr_ast*/ = false) const {
|
2019-09-24 12:52:45 -07:00
|
|
|
desc.DropDestinationBuffer();
|
2019-12-10 15:40:23 -08:00
|
|
|
return TensorBlock(m_leftImpl.block(desc, scratch), m_rightImpl.block(desc, scratch), m_functor);
|
2019-09-24 12:52:45 -07:00
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EvaluatorPointerType data() const { return NULL; }
|
2014-08-13 08:26:44 -07:00
|
|
|
|
2014-04-28 10:32:27 -07:00
|
|
|
private:
|
2019-08-02 11:18:13 -07:00
|
|
|
const Device EIGEN_DEVICE_REF m_device;
|
2014-04-28 10:32:27 -07:00
|
|
|
const BinaryOp m_functor;
|
2014-06-10 09:14:44 -07:00
|
|
|
TensorEvaluator<LeftArgType, Device> m_leftImpl;
|
|
|
|
|
TensorEvaluator<RightArgType, Device> m_rightImpl;
|
2014-04-28 10:32:27 -07:00
|
|
|
};
|
|
|
|
|
|
2016-06-02 17:04:19 -07:00
|
|
|
// -------------------- CwiseTernaryOp --------------------
|
|
|
|
|
|
|
|
|
|
template <typename TernaryOp, typename Arg1Type, typename Arg2Type, typename Arg3Type, typename Device>
|
|
|
|
|
struct TensorEvaluator<const TensorCwiseTernaryOp<TernaryOp, Arg1Type, Arg2Type, Arg3Type>, Device> {
|
|
|
|
|
typedef TensorCwiseTernaryOp<TernaryOp, Arg1Type, Arg2Type, Arg3Type> XprType;
|
|
|
|
|
|
2022-03-16 16:43:40 +00:00
|
|
|
static constexpr int Layout = TensorEvaluator<Arg1Type, Device>::Layout;
|
2016-06-02 17:04:19 -07:00
|
|
|
enum {
|
|
|
|
|
IsAligned = TensorEvaluator<Arg1Type, Device>::IsAligned & TensorEvaluator<Arg2Type, Device>::IsAligned &
|
|
|
|
|
TensorEvaluator<Arg3Type, Device>::IsAligned,
|
2019-10-17 11:17:33 -07:00
|
|
|
PacketAccess = TensorEvaluator<Arg1Type, Device>::PacketAccess && TensorEvaluator<Arg2Type, Device>::PacketAccess &&
|
|
|
|
|
TensorEvaluator<Arg3Type, Device>::PacketAccess && internal::functor_traits<TernaryOp>::PacketAccess,
|
2019-12-10 15:40:23 -08:00
|
|
|
BlockAccess = false,
|
2019-10-17 11:17:33 -07:00
|
|
|
PreferBlockAccess = TensorEvaluator<Arg1Type, Device>::PreferBlockAccess ||
|
|
|
|
|
TensorEvaluator<Arg2Type, Device>::PreferBlockAccess ||
|
|
|
|
|
TensorEvaluator<Arg3Type, Device>::PreferBlockAccess,
|
|
|
|
|
CoordAccess = false, // to be implemented
|
|
|
|
|
RawAccess = false
|
2016-06-02 17:04:19 -07:00
|
|
|
};
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_DEVICE_FUNC TensorEvaluator(const XprType& op, const Device& device)
|
2016-06-02 17:04:19 -07:00
|
|
|
: m_functor(op.functor()),
|
|
|
|
|
m_arg1Impl(op.arg1Expression(), device),
|
|
|
|
|
m_arg2Impl(op.arg2Expression(), device),
|
|
|
|
|
m_arg3Impl(op.arg3Expression(), device) {
|
|
|
|
|
EIGEN_STATIC_ASSERT((static_cast<int>(TensorEvaluator<Arg1Type, Device>::Layout) ==
|
|
|
|
|
static_cast<int>(TensorEvaluator<Arg3Type, Device>::Layout) ||
|
|
|
|
|
internal::traits<XprType>::NumDimensions <= 1),
|
|
|
|
|
YOU_MADE_A_PROGRAMMING_MISTAKE);
|
2016-06-06 07:26:48 -07:00
|
|
|
|
|
|
|
|
EIGEN_STATIC_ASSERT((internal::is_same<typename internal::traits<Arg1Type>::StorageKind,
|
|
|
|
|
typename internal::traits<Arg2Type>::StorageKind>::value),
|
|
|
|
|
STORAGE_KIND_MUST_MATCH)
|
|
|
|
|
EIGEN_STATIC_ASSERT((internal::is_same<typename internal::traits<Arg1Type>::StorageKind,
|
|
|
|
|
typename internal::traits<Arg3Type>::StorageKind>::value),
|
|
|
|
|
STORAGE_KIND_MUST_MATCH)
|
|
|
|
|
EIGEN_STATIC_ASSERT((internal::is_same<typename internal::traits<Arg1Type>::Index,
|
|
|
|
|
typename internal::traits<Arg2Type>::Index>::value),
|
|
|
|
|
STORAGE_INDEX_MUST_MATCH)
|
|
|
|
|
EIGEN_STATIC_ASSERT((internal::is_same<typename internal::traits<Arg1Type>::Index,
|
|
|
|
|
typename internal::traits<Arg3Type>::Index>::value),
|
|
|
|
|
STORAGE_INDEX_MUST_MATCH)
|
|
|
|
|
|
2016-06-02 17:04:19 -07:00
|
|
|
eigen_assert(dimensions_match(m_arg1Impl.dimensions(), m_arg2Impl.dimensions()) &&
|
|
|
|
|
dimensions_match(m_arg1Impl.dimensions(), m_arg3Impl.dimensions()));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
typedef typename XprType::Index Index;
|
|
|
|
|
typedef typename XprType::Scalar Scalar;
|
|
|
|
|
typedef typename internal::traits<XprType>::Scalar CoeffReturnType;
|
|
|
|
|
typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
|
2016-06-02 17:04:19 -07:00
|
|
|
typedef typename TensorEvaluator<Arg1Type, Device>::Dimensions Dimensions;
|
2019-06-28 10:08:23 +01:00
|
|
|
typedef StorageMemory<CoeffReturnType, Device> Storage;
|
|
|
|
|
typedef typename Storage::Type EvaluatorPointerType;
|
2016-06-02 17:04:19 -07:00
|
|
|
|
2019-09-24 12:52:45 -07:00
|
|
|
//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
|
2019-12-10 15:40:23 -08:00
|
|
|
typedef internal::TensorBlockNotImplemented TensorBlock;
|
2019-09-24 12:52:45 -07:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
2016-06-02 17:04:19 -07:00
|
|
|
EIGEN_DEVICE_FUNC const Dimensions& dimensions() const {
|
|
|
|
|
// TODO: use arg2 or arg3 dimensions if they are known at compile time.
|
|
|
|
|
return m_arg1Impl.dimensions();
|
|
|
|
|
}
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType) {
|
2016-06-02 17:04:19 -07:00
|
|
|
m_arg1Impl.evalSubExprsIfNeeded(NULL);
|
|
|
|
|
m_arg2Impl.evalSubExprsIfNeeded(NULL);
|
|
|
|
|
m_arg3Impl.evalSubExprsIfNeeded(NULL);
|
|
|
|
|
return true;
|
|
|
|
|
}
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_STRONG_INLINE void cleanup() {
|
2016-06-02 17:04:19 -07:00
|
|
|
m_arg1Impl.cleanup();
|
|
|
|
|
m_arg2Impl.cleanup();
|
|
|
|
|
m_arg3Impl.cleanup();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC CoeffReturnType coeff(Index index) const {
|
|
|
|
|
return m_functor(m_arg1Impl.coeff(index), m_arg2Impl.coeff(index), m_arg3Impl.coeff(index));
|
|
|
|
|
}
|
|
|
|
|
template <int LoadMode>
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const {
|
|
|
|
|
return m_functor.packetOp(m_arg1Impl.template packet<LoadMode>(index), m_arg2Impl.template packet<LoadMode>(index),
|
|
|
|
|
m_arg3Impl.template packet<LoadMode>(index));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
const double functor_cost = internal::functor_traits<TernaryOp>::Cost;
|
|
|
|
|
return m_arg1Impl.costPerCoeff(vectorized) + m_arg2Impl.costPerCoeff(vectorized) +
|
|
|
|
|
m_arg3Impl.costPerCoeff(vectorized) + TensorOpCost(0, 0, functor_cost, vectorized, PacketSize);
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EvaluatorPointerType data() const { return NULL; }
|
2016-06-02 17:04:19 -07:00
|
|
|
|
|
|
|
|
private:
|
|
|
|
|
const TernaryOp m_functor;
|
|
|
|
|
TensorEvaluator<Arg1Type, Device> m_arg1Impl;
|
2016-09-19 12:44:13 +01:00
|
|
|
TensorEvaluator<Arg2Type, Device> m_arg2Impl;
|
2016-06-02 17:04:19 -07:00
|
|
|
TensorEvaluator<Arg3Type, Device> m_arg3Impl;
|
|
|
|
|
};
|
|
|
|
|
|
2014-05-22 16:22:35 -07:00
|
|
|
// -------------------- SelectOp --------------------
|
|
|
|
|
|
2014-06-10 09:14:44 -07:00
|
|
|
template <typename IfArgType, typename ThenArgType, typename ElseArgType, typename Device>
|
|
|
|
|
struct TensorEvaluator<const TensorSelectOp<IfArgType, ThenArgType, ElseArgType>, Device> {
|
2014-05-22 16:22:35 -07:00
|
|
|
typedef TensorSelectOp<IfArgType, ThenArgType, ElseArgType> XprType;
|
2015-03-25 13:25:53 -07:00
|
|
|
typedef typename XprType::Scalar Scalar;
|
2023-11-29 11:12:48 +00:00
|
|
|
|
2023-04-18 20:52:16 +00:00
|
|
|
using TernarySelectOp = internal::scalar_boolean_select_op<typename internal::traits<ThenArgType>::Scalar,
|
|
|
|
|
typename internal::traits<ElseArgType>::Scalar,
|
|
|
|
|
typename internal::traits<IfArgType>::Scalar>;
|
|
|
|
|
static constexpr bool TernaryPacketAccess =
|
|
|
|
|
TensorEvaluator<ThenArgType, Device>::PacketAccess && TensorEvaluator<ElseArgType, Device>::PacketAccess &&
|
|
|
|
|
TensorEvaluator<IfArgType, Device>::PacketAccess && internal::functor_traits<TernarySelectOp>::PacketAccess;
|
2014-05-22 16:22:35 -07:00
|
|
|
|
2022-03-16 16:43:40 +00:00
|
|
|
static constexpr int Layout = TensorEvaluator<IfArgType, Device>::Layout;
|
2014-05-22 16:22:35 -07:00
|
|
|
enum {
|
2019-10-02 12:44:06 -07:00
|
|
|
IsAligned = TensorEvaluator<ThenArgType, Device>::IsAligned & TensorEvaluator<ElseArgType, Device>::IsAligned,
|
2025-11-03 23:27:50 +00:00
|
|
|
PacketAccess =
|
|
|
|
|
(TensorEvaluator<ThenArgType, Device>::PacketAccess && TensorEvaluator<ElseArgType, Device>::PacketAccess) ||
|
|
|
|
|
TernaryPacketAccess,
|
2019-12-10 15:40:23 -08:00
|
|
|
BlockAccess = TensorEvaluator<IfArgType, Device>::BlockAccess &&
|
|
|
|
|
TensorEvaluator<ThenArgType, Device>::BlockAccess &&
|
|
|
|
|
TensorEvaluator<ElseArgType, Device>::BlockAccess,
|
2019-10-02 12:44:06 -07:00
|
|
|
PreferBlockAccess = TensorEvaluator<IfArgType, Device>::PreferBlockAccess ||
|
|
|
|
|
TensorEvaluator<ThenArgType, Device>::PreferBlockAccess ||
|
|
|
|
|
TensorEvaluator<ElseArgType, Device>::PreferBlockAccess,
|
|
|
|
|
CoordAccess = false, // to be implemented
|
|
|
|
|
RawAccess = false
|
2014-05-22 16:22:35 -07:00
|
|
|
};
|
|
|
|
|
|
2021-05-11 22:47:49 +00:00
|
|
|
EIGEN_DEVICE_FUNC TensorEvaluator(const XprType& op, const Device& device)
|
2014-06-10 09:14:44 -07:00
|
|
|
: m_condImpl(op.ifExpression(), device),
|
|
|
|
|
m_thenImpl(op.thenExpression(), device),
|
|
|
|
|
m_elseImpl(op.elseExpression(), device) {
|
2015-02-10 12:25:02 -08:00
|
|
|
EIGEN_STATIC_ASSERT((static_cast<int>(TensorEvaluator<IfArgType, Device>::Layout) ==
|
|
|
|
|
static_cast<int>(TensorEvaluator<ThenArgType, Device>::Layout)),
|
|
|
|
|
YOU_MADE_A_PROGRAMMING_MISTAKE);
|
|
|
|
|
EIGEN_STATIC_ASSERT((static_cast<int>(TensorEvaluator<IfArgType, Device>::Layout) ==
|
|
|
|
|
static_cast<int>(TensorEvaluator<ElseArgType, Device>::Layout)),
|
|
|
|
|
YOU_MADE_A_PROGRAMMING_MISTAKE);
|
2015-01-14 12:47:46 -08:00
|
|
|
eigen_assert(dimensions_match(m_condImpl.dimensions(), m_thenImpl.dimensions()));
|
|
|
|
|
eigen_assert(dimensions_match(m_thenImpl.dimensions(), m_elseImpl.dimensions()));
|
2014-11-04 10:24:42 -08:00
|
|
|
}
|
2014-05-22 16:22:35 -07:00
|
|
|
|
|
|
|
|
typedef typename XprType::Index Index;
|
2014-10-16 10:41:07 -07:00
|
|
|
typedef typename internal::traits<XprType>::Scalar CoeffReturnType;
|
2016-03-08 12:07:33 -08:00
|
|
|
typedef typename PacketType<CoeffReturnType, Device>::type PacketReturnType;
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int PacketSize = PacketType<CoeffReturnType, Device>::size;
|
2014-06-10 09:14:44 -07:00
|
|
|
typedef typename TensorEvaluator<IfArgType, Device>::Dimensions Dimensions;
|
2019-06-28 10:08:23 +01:00
|
|
|
typedef StorageMemory<CoeffReturnType, Device> Storage;
|
|
|
|
|
typedef typename Storage::Type EvaluatorPointerType;
|
2014-05-22 16:22:35 -07:00
|
|
|
|
2022-04-04 17:33:33 +00:00
|
|
|
static constexpr int NumDims = internal::array_size<Dimensions>::value;
|
2019-10-02 12:44:06 -07:00
|
|
|
|
2019-09-24 12:52:45 -07:00
|
|
|
//===- Tensor block evaluation strategy (see TensorBlock.h) -------------===//
|
2019-10-02 12:44:06 -07:00
|
|
|
typedef internal::TensorBlockDescriptor<NumDims, Index> TensorBlockDesc;
|
|
|
|
|
typedef internal::TensorBlockScratchAllocator<Device> TensorBlockScratch;
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
typedef typename TensorEvaluator<const IfArgType, Device>::TensorBlock IfArgTensorBlock;
|
|
|
|
|
typedef typename TensorEvaluator<const ThenArgType, Device>::TensorBlock ThenArgTensorBlock;
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typedef typename TensorEvaluator<const ElseArgType, Device>::TensorBlock ElseArgTensorBlock;
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2019-10-02 12:44:06 -07:00
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struct TensorSelectOpBlockFactory {
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template <typename IfArgXprType, typename ThenArgXprType, typename ElseArgXprType>
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struct XprType {
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typedef TensorSelectOp<const IfArgXprType, const ThenArgXprType, const ElseArgXprType> type;
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};
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template <typename IfArgXprType, typename ThenArgXprType, typename ElseArgXprType>
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typename XprType<IfArgXprType, ThenArgXprType, ElseArgXprType>::type expr(const IfArgXprType& if_expr,
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const ThenArgXprType& then_expr,
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const ElseArgXprType& else_expr) const {
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return typename XprType<IfArgXprType, ThenArgXprType, ElseArgXprType>::type(if_expr, then_expr, else_expr);
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}
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};
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typedef internal::TensorTernaryExprBlock<TensorSelectOpBlockFactory, IfArgTensorBlock, ThenArgTensorBlock,
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ElseArgTensorBlock>
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2019-12-10 15:40:23 -08:00
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TensorBlock;
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2019-09-24 12:52:45 -07:00
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//===--------------------------------------------------------------------===//
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2014-06-04 09:21:48 -07:00
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EIGEN_DEVICE_FUNC const Dimensions& dimensions() const {
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// TODO: use then or else impl instead if they happen to be known at compile time.
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return m_condImpl.dimensions();
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}
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2014-06-13 09:56:51 -07:00
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2021-05-11 22:47:49 +00:00
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EIGEN_STRONG_INLINE bool evalSubExprsIfNeeded(EvaluatorPointerType) {
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2014-08-13 08:26:44 -07:00
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m_condImpl.evalSubExprsIfNeeded(NULL);
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m_thenImpl.evalSubExprsIfNeeded(NULL);
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m_elseImpl.evalSubExprsIfNeeded(NULL);
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return true;
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2014-06-13 09:56:51 -07:00
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}
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2019-12-09 18:36:13 +00:00
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#ifdef EIGEN_USE_THREADS
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template <typename EvalSubExprsCallback>
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EIGEN_STRONG_INLINE void evalSubExprsIfNeededAsync(EvaluatorPointerType, EvalSubExprsCallback done) {
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m_condImpl.evalSubExprsIfNeeded(nullptr, [this, done](bool) {
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m_thenImpl.evalSubExprsIfNeeded(
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nullptr, [this, done](bool) { m_elseImpl.evalSubExprsIfNeeded(nullptr, [done](bool) { done(true); }); });
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});
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}
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#endif // EIGEN_USE_THREADS
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2021-05-11 22:47:49 +00:00
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EIGEN_STRONG_INLINE void cleanup() {
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2014-06-13 09:56:51 -07:00
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m_condImpl.cleanup();
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m_thenImpl.cleanup();
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m_elseImpl.cleanup();
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}
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2014-05-22 16:22:35 -07:00
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EIGEN_DEVICE_FUNC CoeffReturnType coeff(Index index) const {
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return m_condImpl.coeff(index) ? m_thenImpl.coeff(index) : m_elseImpl.coeff(index);
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}
|
2023-04-18 20:52:16 +00:00
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template <int LoadMode, bool UseTernary = TernaryPacketAccess, std::enable_if_t<!UseTernary, bool> = true>
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2014-10-13 17:02:09 -07:00
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EIGEN_DEVICE_FUNC PacketReturnType packet(Index index) const {
|
2025-11-05 19:44:47 +00:00
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EIGEN_ALIGN_TO_BOUNDARY(sizeof(PacketReturnType)) std::remove_const_t<Scalar> arr[PacketSize];
|
2019-06-28 10:08:23 +01:00
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|
|
EIGEN_UNROLL_LOOP
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|
for (Index i = 0; i < PacketSize; ++i) {
|
2025-11-03 23:27:50 +00:00
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|
arr[i] = m_condImpl.coeff(index + i) ? Scalar(-1) : Scalar(0);
|
2019-06-28 10:08:23 +01:00
|
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|
}
|
2025-11-03 23:27:50 +00:00
|
|
|
return TernarySelectOp().template packetOp<PacketReturnType>(m_thenImpl.template packet<LoadMode>(index),
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|
m_elseImpl.template packet<LoadMode>(index),
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|
internal::pload<PacketReturnType>(arr));
|
2014-05-22 16:22:35 -07:00
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|
}
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|
2023-04-18 20:52:16 +00:00
|
|
|
template <int LoadMode, bool UseTernary = TernaryPacketAccess, std::enable_if_t<UseTernary, bool> = true>
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|
|
|
|
EIGEN_DEVICE_FUNC PacketReturnType packet(Index index) const {
|
|
|
|
|
return TernarySelectOp().template packetOp<PacketReturnType>(m_thenImpl.template packet<LoadMode>(index),
|
|
|
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|
m_elseImpl.template packet<LoadMode>(index),
|
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|
|
|
m_condImpl.template packet<LoadMode>(index));
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|
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|
}
|
|
|
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|
|
2016-04-14 13:57:35 -07:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorOpCost costPerCoeff(bool vectorized) const {
|
|
|
|
|
return m_condImpl.costPerCoeff(vectorized) +
|
|
|
|
|
m_thenImpl.costPerCoeff(vectorized).cwiseMax(m_elseImpl.costPerCoeff(vectorized));
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE internal::TensorBlockResourceRequirements getResourceRequirements() const {
|
2019-12-18 20:07:00 +00:00
|
|
|
auto then_req = m_thenImpl.getResourceRequirements();
|
|
|
|
|
auto else_req = m_elseImpl.getResourceRequirements();
|
|
|
|
|
|
|
|
|
|
auto merged_req = internal::TensorBlockResourceRequirements::merge(then_req, else_req);
|
|
|
|
|
merged_req.cost_per_coeff = then_req.cost_per_coeff.cwiseMax(else_req.cost_per_coeff);
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
return internal::TensorBlockResourceRequirements::merge(m_condImpl.getResourceRequirements(), merged_req);
|
2019-10-02 12:44:06 -07:00
|
|
|
}
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE TensorBlock block(TensorBlockDesc& desc, TensorBlockScratch& scratch,
|
2019-10-14 14:31:59 -07:00
|
|
|
bool /*root_of_expr_ast*/ = false) const {
|
2019-10-02 12:44:06 -07:00
|
|
|
// It's unsafe to pass destination buffer to underlying expressions, because
|
|
|
|
|
// output might be aliased with one of the inputs.
|
|
|
|
|
desc.DropDestinationBuffer();
|
|
|
|
|
|
2019-12-10 15:40:23 -08:00
|
|
|
return TensorBlock(m_condImpl.block(desc, scratch), m_thenImpl.block(desc, scratch),
|
|
|
|
|
m_elseImpl.block(desc, scratch), TensorSelectOpBlockFactory());
|
2019-10-02 12:44:06 -07:00
|
|
|
}
|
|
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE EvaluatorPointerType data() const { return NULL; }
|
2014-08-13 08:26:44 -07:00
|
|
|
|
2019-06-28 10:08:23 +01:00
|
|
|
#ifdef EIGEN_USE_SYCL
|
|
|
|
|
// binding placeholder accessors to a command group handler for SYCL
|
|
|
|
|
EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void bind(cl::sycl::handler& cgh) const {
|
|
|
|
|
m_condImpl.bind(cgh);
|
|
|
|
|
m_thenImpl.bind(cgh);
|
|
|
|
|
m_elseImpl.bind(cgh);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2014-05-22 16:22:35 -07:00
|
|
|
private:
|
2014-06-10 09:14:44 -07:00
|
|
|
TensorEvaluator<IfArgType, Device> m_condImpl;
|
|
|
|
|
TensorEvaluator<ThenArgType, Device> m_thenImpl;
|
|
|
|
|
TensorEvaluator<ElseArgType, Device> m_elseImpl;
|
2014-05-22 16:22:35 -07:00
|
|
|
};
|
|
|
|
|
|
2014-04-28 10:32:27 -07:00
|
|
|
} // end namespace Eigen
|
|
|
|
|
|
2023-01-16 07:04:08 +00:00
|
|
|
#if defined(EIGEN_USE_SYCL) && defined(SYCL_COMPILER_IS_DPCPP)
|
|
|
|
|
template <typename Derived, typename Device>
|
|
|
|
|
struct cl::sycl::is_device_copyable<
|
|
|
|
|
Eigen::TensorEvaluator<Derived, Device>,
|
|
|
|
|
std::enable_if_t<!std::is_trivially_copyable<Eigen::TensorEvaluator<Derived, Device>>::value>> : std::true_type {};
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-04-28 10:32:27 -07:00
|
|
|
#endif // EIGEN_CXX11_TENSOR_TENSOR_EVALUATOR_H
|