2018-12-06 15:58:06 +01:00
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// This file is part of Eigen, a lightweight C++ template library
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// for linear algebra.
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//
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// Copyright (C) 2018 Gael Guennebaud <gael.guennebaud@inria.fr>
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//
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// This Source Code Form is subject to the terms of the Mozilla
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// Public License v. 2.0. If a copy of the MPL was not distributed
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// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
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#ifndef EIGEN_COMPLEX_AVX512_H
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#define EIGEN_COMPLEX_AVX512_H
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2021-09-10 19:12:26 +00:00
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#include "../../InternalHeaderCheck.h"
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2018-12-06 15:58:06 +01:00
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namespace Eigen {
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namespace internal {
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//---------- float ----------
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struct Packet8cf
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{
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EIGEN_STRONG_INLINE Packet8cf() {}
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EIGEN_STRONG_INLINE explicit Packet8cf(const __m512& a) : v(a) {}
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__m512 v;
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};
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template<> struct packet_traits<std::complex<float> > : default_packet_traits
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{
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typedef Packet8cf type;
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typedef Packet4cf half;
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enum {
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Vectorizable = 1,
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AlignedOnScalar = 1,
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size = 8,
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HasHalfPacket = 1,
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HasAdd = 1,
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HasSub = 1,
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HasMul = 1,
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HasDiv = 1,
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HasNegate = 1,
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2020-12-08 18:13:35 -08:00
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HasSqrt = 1,
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2018-12-06 15:58:06 +01:00
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HasAbs = 0,
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HasAbs2 = 0,
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HasMin = 0,
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HasMax = 0,
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2020-05-11 13:23:31 -07:00
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HasSetLinear = 0
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2018-12-06 15:58:06 +01:00
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};
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};
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template<> struct unpacket_traits<Packet8cf> {
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typedef std::complex<float> type;
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2020-12-08 18:13:35 -08:00
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typedef Packet4cf half;
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typedef Packet16f as_real;
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2018-12-06 15:58:06 +01:00
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enum {
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size = 8,
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Introducing "vectorized" byte on unpacket_traits structs
This is a preparation to a change on gebp_traits, where a new template
argument will be introduced to dictate the packet size, so it won't be
bound to the current/max packet size only anymore.
By having packet types defined early on gebp_traits, one has now to
act on packet types, not scalars anymore, for the enum values defined
on that class. One approach for reaching the vectorizable/size
properties one needs there could be getting the packet's scalar again
with unpacket_traits<>, then the size/Vectorizable enum entries from
packet_traits<>. It turns out guards like "#ifndef
EIGEN_VECTORIZE_AVX512" at AVX/PacketMath.h will hide smaller packet
variations of packet_traits<> for some types (and it makes sense to
keep that). In other words, one can't go back to the scalar and create
a new PacketType, as this will always lead to the maximum packet type
for the architecture.
The less costly/invasive solution for that, thus, is to add the
vectorizable info on every unpacket_traits struct as well.
2018-12-19 14:24:44 -08:00
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alignment=unpacket_traits<Packet16f>::alignment,
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Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
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vectorizable=true,
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2019-05-02 14:52:58 -07:00
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masked_load_available=false,
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masked_store_available=false
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2018-12-06 15:58:06 +01:00
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};
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};
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2019-01-16 14:43:33 -08:00
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template<> EIGEN_STRONG_INLINE Packet8cf ptrue<Packet8cf>(const Packet8cf& a) { return Packet8cf(ptrue(Packet16f(a.v))); }
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2018-12-06 15:58:06 +01:00
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template<> EIGEN_STRONG_INLINE Packet8cf padd<Packet8cf>(const Packet8cf& a, const Packet8cf& b) { return Packet8cf(_mm512_add_ps(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet8cf psub<Packet8cf>(const Packet8cf& a, const Packet8cf& b) { return Packet8cf(_mm512_sub_ps(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet8cf pnegate(const Packet8cf& a)
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{
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return Packet8cf(pnegate(a.v));
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}
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template<> EIGEN_STRONG_INLINE Packet8cf pconj(const Packet8cf& a)
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{
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const __m512 mask = _mm512_castsi512_ps(_mm512_setr_epi32(
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0x00000000,0x80000000,0x00000000,0x80000000,0x00000000,0x80000000,0x00000000,0x80000000,
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0x00000000,0x80000000,0x00000000,0x80000000,0x00000000,0x80000000,0x00000000,0x80000000));
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2019-01-03 14:33:04 +01:00
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return Packet8cf(pxor(a.v,mask));
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2018-12-06 15:58:06 +01:00
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}
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template<> EIGEN_STRONG_INLINE Packet8cf pmul<Packet8cf>(const Packet8cf& a, const Packet8cf& b)
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{
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__m512 tmp2 = _mm512_mul_ps(_mm512_movehdup_ps(a.v), _mm512_permute_ps(b.v, _MM_SHUFFLE(2,3,0,1)));
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return Packet8cf(_mm512_fmaddsub_ps(_mm512_moveldup_ps(a.v), b.v, tmp2));
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}
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2019-01-03 14:33:04 +01:00
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template<> EIGEN_STRONG_INLINE Packet8cf pand <Packet8cf>(const Packet8cf& a, const Packet8cf& b) { return Packet8cf(pand(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet8cf por <Packet8cf>(const Packet8cf& a, const Packet8cf& b) { return Packet8cf(por(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet8cf pxor <Packet8cf>(const Packet8cf& a, const Packet8cf& b) { return Packet8cf(pxor(a.v,b.v)); }
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template<> EIGEN_STRONG_INLINE Packet8cf pandnot<Packet8cf>(const Packet8cf& a, const Packet8cf& b) { return Packet8cf(pandnot(a.v,b.v)); }
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2018-12-06 15:58:06 +01:00
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2019-01-07 16:53:36 -08:00
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template <>
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EIGEN_STRONG_INLINE Packet8cf pcmp_eq(const Packet8cf& a, const Packet8cf& b) {
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__m512 eq = pcmp_eq<Packet16f>(a.v, b.v);
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2019-01-09 16:34:23 -08:00
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return Packet8cf(pand(eq, _mm512_permute_ps(eq, 0xB1)));
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2019-01-07 16:53:36 -08:00
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}
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2018-12-06 15:58:06 +01:00
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template<> EIGEN_STRONG_INLINE Packet8cf pload <Packet8cf>(const std::complex<float>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet8cf(pload<Packet16f>(&numext::real_ref(*from))); }
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template<> EIGEN_STRONG_INLINE Packet8cf ploadu<Packet8cf>(const std::complex<float>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet8cf(ploadu<Packet16f>(&numext::real_ref(*from))); }
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template<> EIGEN_STRONG_INLINE Packet8cf pset1<Packet8cf>(const std::complex<float>& from)
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{
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2021-09-17 12:49:01 -07:00
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const float re = std::real(from);
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const float im = std::imag(from);
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return Packet8cf(_mm512_set_ps(im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re));
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2018-12-06 15:58:06 +01:00
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}
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template<> EIGEN_STRONG_INLINE Packet8cf ploaddup<Packet8cf>(const std::complex<float>* from)
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{
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return Packet8cf( _mm512_castpd_ps( ploaddup<Packet8d>((const double*)(const void*)from )) );
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}
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template<> EIGEN_STRONG_INLINE Packet8cf ploadquad<Packet8cf>(const std::complex<float>* from)
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{
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return Packet8cf( _mm512_castpd_ps( ploadquad<Packet8d>((const double*)(const void*)from )) );
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}
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template<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float>* to, const Packet8cf& from) { EIGEN_DEBUG_ALIGNED_STORE pstore(&numext::real_ref(*to), from.v); }
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template<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float>* to, const Packet8cf& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu(&numext::real_ref(*to), from.v); }
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template<> EIGEN_DEVICE_FUNC inline Packet8cf pgather<std::complex<float>, Packet8cf>(const std::complex<float>* from, Index stride)
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{
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return Packet8cf(_mm512_castpd_ps(pgather<double,Packet8d>((const double*)(const void*)from, stride)));
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}
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template<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet8cf>(std::complex<float>* to, const Packet8cf& from, Index stride)
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{
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pscatter((double*)(void*)to, _mm512_castps_pd(from.v), stride);
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}
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template<> EIGEN_STRONG_INLINE std::complex<float> pfirst<Packet8cf>(const Packet8cf& a)
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{
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return pfirst(Packet2cf(_mm512_castps512_ps128(a.v)));
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}
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template<> EIGEN_STRONG_INLINE Packet8cf preverse(const Packet8cf& a) {
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return Packet8cf(_mm512_castsi512_ps(
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_mm512_permutexvar_epi64( _mm512_set_epi32(0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7),
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_mm512_castps_si512(a.v))));
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}
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template<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet8cf>(const Packet8cf& a)
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{
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2019-01-03 14:33:04 +01:00
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return predux(padd(Packet4cf(extract256<0>(a.v)),
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Packet4cf(extract256<1>(a.v))));
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2018-12-06 15:58:06 +01:00
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}
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template<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet8cf>(const Packet8cf& a)
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{
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2019-01-03 14:33:04 +01:00
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return predux_mul(pmul(Packet4cf(extract256<0>(a.v)),
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Packet4cf(extract256<1>(a.v))));
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2018-12-06 15:58:06 +01:00
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}
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template <>
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EIGEN_STRONG_INLINE Packet4cf predux_half_dowto4<Packet8cf>(const Packet8cf& a) {
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2019-01-03 14:33:04 +01:00
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__m256 lane0 = extract256<0>(a.v);
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__m256 lane1 = extract256<1>(a.v);
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2018-12-06 15:58:06 +01:00
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__m256 res = _mm256_add_ps(lane0, lane1);
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return Packet4cf(res);
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}
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EIGEN_MAKE_CONJ_HELPER_CPLX_REAL(Packet8cf,Packet16f)
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template<> EIGEN_STRONG_INLINE Packet8cf pdiv<Packet8cf>(const Packet8cf& a, const Packet8cf& b)
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{
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2021-06-30 15:53:06 -07:00
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return pdiv_complex(a, b);
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2018-12-06 15:58:06 +01:00
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}
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template<> EIGEN_STRONG_INLINE Packet8cf pcplxflip<Packet8cf>(const Packet8cf& x)
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{
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return Packet8cf(_mm512_shuffle_ps(x.v, x.v, _MM_SHUFFLE(2, 3, 0 ,1)));
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}
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//---------- double ----------
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struct Packet4cd
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{
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EIGEN_STRONG_INLINE Packet4cd() {}
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EIGEN_STRONG_INLINE explicit Packet4cd(const __m512d& a) : v(a) {}
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__m512d v;
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};
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template<> struct packet_traits<std::complex<double> > : default_packet_traits
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{
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typedef Packet4cd type;
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typedef Packet2cd half;
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enum {
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Vectorizable = 1,
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AlignedOnScalar = 0,
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size = 4,
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HasHalfPacket = 1,
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HasAdd = 1,
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HasSub = 1,
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HasMul = 1,
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HasDiv = 1,
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HasNegate = 1,
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2020-12-08 18:13:35 -08:00
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HasSqrt = 1,
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2018-12-06 15:58:06 +01:00
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HasAbs = 0,
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HasAbs2 = 0,
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HasMin = 0,
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HasMax = 0,
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2020-05-07 17:14:26 -07:00
|
|
|
HasSetLinear = 0
|
2018-12-06 15:58:06 +01:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template<> struct unpacket_traits<Packet4cd> {
|
|
|
|
|
typedef std::complex<double> type;
|
2020-12-08 18:13:35 -08:00
|
|
|
typedef Packet2cd half;
|
|
|
|
|
typedef Packet8d as_real;
|
2018-12-06 15:58:06 +01:00
|
|
|
enum {
|
|
|
|
|
size = 4,
|
Introducing "vectorized" byte on unpacket_traits structs
This is a preparation to a change on gebp_traits, where a new template
argument will be introduced to dictate the packet size, so it won't be
bound to the current/max packet size only anymore.
By having packet types defined early on gebp_traits, one has now to
act on packet types, not scalars anymore, for the enum values defined
on that class. One approach for reaching the vectorizable/size
properties one needs there could be getting the packet's scalar again
with unpacket_traits<>, then the size/Vectorizable enum entries from
packet_traits<>. It turns out guards like "#ifndef
EIGEN_VECTORIZE_AVX512" at AVX/PacketMath.h will hide smaller packet
variations of packet_traits<> for some types (and it makes sense to
keep that). In other words, one can't go back to the scalar and create
a new PacketType, as this will always lead to the maximum packet type
for the architecture.
The less costly/invasive solution for that, thus, is to add the
vectorizable info on every unpacket_traits struct as well.
2018-12-19 14:24:44 -08:00
|
|
|
alignment = unpacket_traits<Packet8d>::alignment,
|
Adding lowlevel APIs for optimized RHS packet load in TensorFlow
SpatialConvolution
Low-level APIs are added in order to optimized packet load in gemm_pack_rhs
in TensorFlow SpatialConvolution. The optimization is for scenario when a
packet is split across 2 adjacent columns. In this case we read it as two
'partial' packets and then merge these into 1. Currently this only works for
Packet16f (AVX512) and Packet8f (AVX2). We plan to add this for other
packet types (such as Packet8d) also.
This optimization shows significant speedup in SpatialConvolution with
certain parameters. Some examples are below.
Benchmark parameters are specified as:
Batch size, Input dim, Depth, Num of filters, Filter dim
Speedup numbers are specified for number of threads 1, 2, 4, 8, 16.
AVX512:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 |2.18X, 2.13X, 1.73X, 1.64X, 1.66X
128, 24x24, 1, 64, 8x8 |2.00X, 1.98X, 1.93X, 1.91X, 1.91X
32, 24x24, 3, 64, 5x5 |2.26X, 2.14X, 2.17X, 2.22X, 2.33X
128, 24x24, 3, 64, 3x3 |1.51X, 1.45X, 1.45X, 1.67X, 1.57X
32, 14x14, 24, 64, 5x5 |1.21X, 1.19X, 1.16X, 1.70X, 1.17X
128, 128x128, 3, 96, 11x11 |2.17X, 2.18X, 2.19X, 2.20X, 2.18X
AVX2:
Parameters | Speedup (Num of threads: 1, 2, 4, 8, 16)
----------------------------|------------------------------------------
128, 24x24, 3, 64, 5x5 | 1.66X, 1.65X, 1.61X, 1.56X, 1.49X
32, 24x24, 3, 64, 5x5 | 1.71X, 1.63X, 1.77X, 1.58X, 1.68X
128, 24x24, 1, 64, 5x5 | 1.44X, 1.40X, 1.38X, 1.37X, 1.33X
128, 24x24, 3, 64, 3x3 | 1.68X, 1.63X, 1.58X, 1.56X, 1.62X
128, 128x128, 3, 96, 11x11 | 1.36X, 1.36X, 1.37X, 1.37X, 1.37X
In the higher level benchmark cifar10, we observe a runtime improvement
of around 6% for AVX512 on Intel Skylake server (8 cores).
On lower level PackRhs micro-benchmarks specified in TensorFlow
tensorflow/core/kernels/eigen_spatial_convolutions_test.cc, we observe
the following runtime numbers:
AVX512:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 41350 | 15073 | 2.74X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 7277 | 7341 | 0.99X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 8675 | 8681 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 24155 | 16079 | 1.50X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 25052 | 17152 | 1.46X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 18269 | 18345 | 1.00X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 19468 | 19872 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 156060 | 42432 | 3.68X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 132701 | 36944 | 3.59X
AVX2:
Parameters | Runtime without patch (ns) | Runtime with patch (ns) | Speedup
---------------------------------------------------------------|----------------------------|-------------------------|---------
BM_RHS_NAME(PackRhs, 128, 24, 24, 3, 64, 5, 5, 1, 1, 256, 56) | 26233 | 12393 | 2.12X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 1, 1, 256, 56) | 6091 | 6062 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 32, 64, 5, 5, 2, 2, 256, 56) | 7427 | 7408 | 1.00X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 1, 1, 256, 56) | 23453 | 20826 | 1.13X
BM_RHS_NAME(PackRhs, 32, 64, 64, 30, 64, 5, 5, 2, 2, 256, 56) | 23167 | 22091 | 1.09X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 1, 1, 256, 56) | 23422 | 23682 | 0.99X
BM_RHS_NAME(PackRhs, 32, 256, 256, 4, 16, 8, 8, 2, 4, 256, 56) | 23165 | 23663 | 0.98X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 1, 1, 36, 432) | 72689 | 44969 | 1.62X
BM_RHS_NAME(PackRhs, 32, 64, 64, 4, 16, 3, 3, 2, 2, 36, 432) | 61732 | 39779 | 1.55X
All benchmarks on Intel Skylake server with 8 cores.
2019-04-20 06:46:43 +00:00
|
|
|
vectorizable=true,
|
2019-05-02 14:52:58 -07:00
|
|
|
masked_load_available=false,
|
|
|
|
|
masked_store_available=false
|
2018-12-06 15:58:06 +01:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd padd<Packet4cd>(const Packet4cd& a, const Packet4cd& b) { return Packet4cd(_mm512_add_pd(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd psub<Packet4cd>(const Packet4cd& a, const Packet4cd& b) { return Packet4cd(_mm512_sub_pd(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pnegate(const Packet4cd& a) { return Packet4cd(pnegate(a.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pconj(const Packet4cd& a)
|
|
|
|
|
{
|
|
|
|
|
const __m512d mask = _mm512_castsi512_pd(
|
|
|
|
|
_mm512_set_epi32(0x80000000,0x0,0x0,0x0,0x80000000,0x0,0x0,0x0,
|
|
|
|
|
0x80000000,0x0,0x0,0x0,0x80000000,0x0,0x0,0x0));
|
2018-12-06 18:11:07 +01:00
|
|
|
return Packet4cd(pxor(a.v,mask));
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pmul<Packet4cd>(const Packet4cd& a, const Packet4cd& b)
|
|
|
|
|
{
|
|
|
|
|
__m512d tmp1 = _mm512_shuffle_pd(a.v,a.v,0x0);
|
|
|
|
|
__m512d tmp2 = _mm512_shuffle_pd(a.v,a.v,0xFF);
|
|
|
|
|
__m512d tmp3 = _mm512_shuffle_pd(b.v,b.v,0x55);
|
|
|
|
|
__m512d odd = _mm512_mul_pd(tmp2, tmp3);
|
|
|
|
|
return Packet4cd(_mm512_fmaddsub_pd(tmp1, b.v, odd));
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-16 14:43:33 -08:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd ptrue<Packet4cd>(const Packet4cd& a) { return Packet4cd(ptrue(Packet8d(a.v))); }
|
2019-01-03 14:33:04 +01:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pand <Packet4cd>(const Packet4cd& a, const Packet4cd& b) { return Packet4cd(pand(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd por <Packet4cd>(const Packet4cd& a, const Packet4cd& b) { return Packet4cd(por(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pxor <Packet4cd>(const Packet4cd& a, const Packet4cd& b) { return Packet4cd(pxor(a.v,b.v)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pandnot<Packet4cd>(const Packet4cd& a, const Packet4cd& b) { return Packet4cd(pandnot(a.v,b.v)); }
|
2018-12-06 15:58:06 +01:00
|
|
|
|
2019-01-07 16:53:36 -08:00
|
|
|
template <>
|
|
|
|
|
EIGEN_STRONG_INLINE Packet4cd pcmp_eq(const Packet4cd& a, const Packet4cd& b) {
|
|
|
|
|
__m512d eq = pcmp_eq<Packet8d>(a.v, b.v);
|
2019-01-09 16:34:23 -08:00
|
|
|
return Packet4cd(pand(eq, _mm512_permute_pd(eq, 0x55)));
|
2019-01-07 16:53:36 -08:00
|
|
|
}
|
|
|
|
|
|
2018-12-06 15:58:06 +01:00
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pload <Packet4cd>(const std::complex<double>* from)
|
|
|
|
|
{ EIGEN_DEBUG_ALIGNED_LOAD return Packet4cd(pload<Packet8d>((const double*)from)); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd ploadu<Packet4cd>(const std::complex<double>* from)
|
|
|
|
|
{ EIGEN_DEBUG_UNALIGNED_LOAD return Packet4cd(ploadu<Packet8d>((const double*)from)); }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pset1<Packet4cd>(const std::complex<double>& from)
|
|
|
|
|
{
|
|
|
|
|
return Packet4cd(_mm512_castps_pd(_mm512_broadcast_f32x4( _mm_castpd_ps(pset1<Packet1cd>(from).v))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd ploaddup<Packet4cd>(const std::complex<double>* from) {
|
|
|
|
|
return Packet4cd(_mm512_insertf64x4(
|
|
|
|
|
_mm512_castpd256_pd512(ploaddup<Packet2cd>(from).v), ploaddup<Packet2cd>(from+1).v, 1));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> * to, const Packet4cd& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((double*)to, from.v); }
|
|
|
|
|
template<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> * to, const Packet4cd& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((double*)to, from.v); }
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_DEVICE_FUNC inline Packet4cd pgather<std::complex<double>, Packet4cd>(const std::complex<double>* from, Index stride)
|
|
|
|
|
{
|
|
|
|
|
return Packet4cd(_mm512_insertf64x4(_mm512_castpd256_pd512(
|
2019-01-14 17:57:28 +01:00
|
|
|
_mm256_insertf128_pd(_mm256_castpd128_pd256(ploadu<Packet1cd>(from+0*stride).v), ploadu<Packet1cd>(from+1*stride).v,1)),
|
|
|
|
|
_mm256_insertf128_pd(_mm256_castpd128_pd256(ploadu<Packet1cd>(from+2*stride).v), ploadu<Packet1cd>(from+3*stride).v,1), 1));
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<double>, Packet4cd>(std::complex<double>* to, const Packet4cd& from, Index stride)
|
|
|
|
|
{
|
|
|
|
|
__m512i fromi = _mm512_castpd_si512(from.v);
|
|
|
|
|
double* tod = (double*)(void*)to;
|
2019-01-14 17:57:28 +01:00
|
|
|
_mm_storeu_pd(tod+0*stride, _mm_castsi128_pd(_mm512_extracti32x4_epi32(fromi,0)) );
|
|
|
|
|
_mm_storeu_pd(tod+2*stride, _mm_castsi128_pd(_mm512_extracti32x4_epi32(fromi,1)) );
|
|
|
|
|
_mm_storeu_pd(tod+4*stride, _mm_castsi128_pd(_mm512_extracti32x4_epi32(fromi,2)) );
|
|
|
|
|
_mm_storeu_pd(tod+6*stride, _mm_castsi128_pd(_mm512_extracti32x4_epi32(fromi,3)) );
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<double> pfirst<Packet4cd>(const Packet4cd& a)
|
|
|
|
|
{
|
2019-01-03 14:33:04 +01:00
|
|
|
__m128d low = extract128<0>(a.v);
|
2018-12-06 15:58:06 +01:00
|
|
|
EIGEN_ALIGN16 double res[2];
|
|
|
|
|
_mm_store_pd(res, low);
|
|
|
|
|
return std::complex<double>(res[0],res[1]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd preverse(const Packet4cd& a) {
|
2020-11-18 00:24:19 +00:00
|
|
|
return Packet4cd(_mm512_shuffle_f64x2(a.v, a.v, (shuffle_mask<3,2,1,0>::mask)));
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet4cd>(const Packet4cd& a)
|
|
|
|
|
{
|
|
|
|
|
return predux(padd(Packet2cd(_mm512_extractf64x4_pd(a.v,0)),
|
|
|
|
|
Packet2cd(_mm512_extractf64x4_pd(a.v,1))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet4cd>(const Packet4cd& a)
|
|
|
|
|
{
|
|
|
|
|
return predux_mul(pmul(Packet2cd(_mm512_extractf64x4_pd(a.v,0)),
|
|
|
|
|
Packet2cd(_mm512_extractf64x4_pd(a.v,1))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_MAKE_CONJ_HELPER_CPLX_REAL(Packet4cd,Packet8d)
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pdiv<Packet4cd>(const Packet4cd& a, const Packet4cd& b)
|
|
|
|
|
{
|
2021-06-30 15:53:06 -07:00
|
|
|
return pdiv_complex(a, b);
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<> EIGEN_STRONG_INLINE Packet4cd pcplxflip<Packet4cd>(const Packet4cd& x)
|
|
|
|
|
{
|
|
|
|
|
return Packet4cd(_mm512_permute_pd(x.v,0x55));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC inline void
|
|
|
|
|
ptranspose(PacketBlock<Packet8cf,4>& kernel) {
|
2019-01-11 14:02:09 +01:00
|
|
|
PacketBlock<Packet8d,4> pb;
|
|
|
|
|
|
|
|
|
|
pb.packet[0] = _mm512_castps_pd(kernel.packet[0].v);
|
|
|
|
|
pb.packet[1] = _mm512_castps_pd(kernel.packet[1].v);
|
|
|
|
|
pb.packet[2] = _mm512_castps_pd(kernel.packet[2].v);
|
|
|
|
|
pb.packet[3] = _mm512_castps_pd(kernel.packet[3].v);
|
|
|
|
|
ptranspose(pb);
|
|
|
|
|
kernel.packet[0].v = _mm512_castpd_ps(pb.packet[0]);
|
|
|
|
|
kernel.packet[1].v = _mm512_castpd_ps(pb.packet[1]);
|
|
|
|
|
kernel.packet[2].v = _mm512_castpd_ps(pb.packet[2]);
|
|
|
|
|
kernel.packet[3].v = _mm512_castpd_ps(pb.packet[3]);
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC inline void
|
|
|
|
|
ptranspose(PacketBlock<Packet8cf,8>& kernel) {
|
2019-01-11 14:02:09 +01:00
|
|
|
PacketBlock<Packet8d,8> pb;
|
|
|
|
|
|
|
|
|
|
pb.packet[0] = _mm512_castps_pd(kernel.packet[0].v);
|
|
|
|
|
pb.packet[1] = _mm512_castps_pd(kernel.packet[1].v);
|
|
|
|
|
pb.packet[2] = _mm512_castps_pd(kernel.packet[2].v);
|
|
|
|
|
pb.packet[3] = _mm512_castps_pd(kernel.packet[3].v);
|
|
|
|
|
pb.packet[4] = _mm512_castps_pd(kernel.packet[4].v);
|
|
|
|
|
pb.packet[5] = _mm512_castps_pd(kernel.packet[5].v);
|
|
|
|
|
pb.packet[6] = _mm512_castps_pd(kernel.packet[6].v);
|
|
|
|
|
pb.packet[7] = _mm512_castps_pd(kernel.packet[7].v);
|
|
|
|
|
ptranspose(pb);
|
|
|
|
|
kernel.packet[0].v = _mm512_castpd_ps(pb.packet[0]);
|
|
|
|
|
kernel.packet[1].v = _mm512_castpd_ps(pb.packet[1]);
|
|
|
|
|
kernel.packet[2].v = _mm512_castpd_ps(pb.packet[2]);
|
|
|
|
|
kernel.packet[3].v = _mm512_castpd_ps(pb.packet[3]);
|
|
|
|
|
kernel.packet[4].v = _mm512_castpd_ps(pb.packet[4]);
|
|
|
|
|
kernel.packet[5].v = _mm512_castpd_ps(pb.packet[5]);
|
|
|
|
|
kernel.packet[6].v = _mm512_castpd_ps(pb.packet[6]);
|
|
|
|
|
kernel.packet[7].v = _mm512_castpd_ps(pb.packet[7]);
|
2018-12-06 15:58:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
EIGEN_DEVICE_FUNC inline void
|
|
|
|
|
ptranspose(PacketBlock<Packet4cd,4>& kernel) {
|
2020-11-18 00:24:19 +00:00
|
|
|
__m512d T0 = _mm512_shuffle_f64x2(kernel.packet[0].v, kernel.packet[1].v, (shuffle_mask<0,1,0,1>::mask)); // [a0 a1 b0 b1]
|
|
|
|
|
__m512d T1 = _mm512_shuffle_f64x2(kernel.packet[0].v, kernel.packet[1].v, (shuffle_mask<2,3,2,3>::mask)); // [a2 a3 b2 b3]
|
|
|
|
|
__m512d T2 = _mm512_shuffle_f64x2(kernel.packet[2].v, kernel.packet[3].v, (shuffle_mask<0,1,0,1>::mask)); // [c0 c1 d0 d1]
|
|
|
|
|
__m512d T3 = _mm512_shuffle_f64x2(kernel.packet[2].v, kernel.packet[3].v, (shuffle_mask<2,3,2,3>::mask)); // [c2 c3 d2 d3]
|
|
|
|
|
|
|
|
|
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kernel.packet[3] = Packet4cd(_mm512_shuffle_f64x2(T1, T3, (shuffle_mask<1,3,1,3>::mask))); // [a3 b3 c3 d3]
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kernel.packet[2] = Packet4cd(_mm512_shuffle_f64x2(T1, T3, (shuffle_mask<0,2,0,2>::mask))); // [a2 b2 c2 d2]
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kernel.packet[1] = Packet4cd(_mm512_shuffle_f64x2(T0, T2, (shuffle_mask<1,3,1,3>::mask))); // [a1 b1 c1 d1]
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kernel.packet[0] = Packet4cd(_mm512_shuffle_f64x2(T0, T2, (shuffle_mask<0,2,0,2>::mask))); // [a0 b0 c0 d0]
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2018-12-06 15:58:06 +01:00
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}
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2020-12-08 18:13:35 -08:00
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template<> EIGEN_STRONG_INLINE Packet4cd psqrt<Packet4cd>(const Packet4cd& a) {
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return psqrt_complex<Packet4cd>(a);
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}
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template<> EIGEN_STRONG_INLINE Packet8cf psqrt<Packet8cf>(const Packet8cf& a) {
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return psqrt_complex<Packet8cf>(a);
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}
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2020-11-24 12:57:28 -08:00
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2020-12-08 18:13:35 -08:00
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} // end namespace internal
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2018-12-06 15:58:06 +01:00
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} // end namespace Eigen
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#endif // EIGEN_COMPLEX_AVX512_H
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